公开(公告)号：US06261905B1

公开(公告)日：2001-07-17

申请号：US09560625

申请日：2000-04-28

申请人： Jong Chen ,  Chrong-Jong Lin ,  Hung-Der Su ,  Wen-Ting Chu

发明人： Jong Chen ,  Chrong-Jong Lin ,  Hung-Der Su ,  Wen-Ting Chu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then subtractively etching to form a floating gate followed by the depositing of a second polysilicon layer separated by an intervening inter-gate dielectric layer over the floating gate. On the contrary, a trench is formed in a nitride layer formed over a substrate using a modified damascene process. The first polysilicon layer is conformally deposited into the damascene-like trench to form the floating gate of the disclosed cell. Then, a layer of inter-gate dielectric layer is formed over the first polysilicon layer in the trench, followed by the forming of a second polysilicon layer over the dielectric layer, thus forming the damascene-like stacked gate of this invention. The disclosed method alleviates the problem of having poly residues resulting from defects caused by etching the conventionally deposited polysilicon layer. Furthermore, etching over active region can also cause damage to the underlying substrate, which is not the case here. In addition, the method enables the incorporation of the curved structure of the floating gate of this invention into the area that increases the coupling ratio of the flash memory cell.

摘要翻译： 公开了一种闪存单元及其制造方法，其中电池具有镶嵌式堆叠栅极。 层叠栅极不是通过覆盖沉积第一多晶硅层而形成的，然后进行减法蚀刻以形成浮置栅极，随后沉积由浮置栅极上的中间栅介质层分隔开的第二多晶硅层。 相反，使用改进的镶嵌工艺在形成在衬底上的氮化物层中形成沟槽。 第一多晶硅层被共形沉积到镶嵌状沟槽中以形成所公开电池的浮动栅极。 然后，在沟槽中的第一多晶硅层上方形成栅极间电介质层，随后在电介质层上形成第二多晶硅层，从而形成本发明的镶嵌层状堆叠栅极。 所公开的方法减轻了由通过蚀刻常规沉积的多晶硅层引起的缺陷产生的多余残留物的问题。 此外，在有源区上的蚀刻也可能对下面的衬底造成损害，这在这里不是这种情况。 此外，该方法使得能够将本发明的浮动栅极的弯曲结构结合到增加闪存单元的耦合比的区域中。

公开(公告)号：US06348382B1

公开(公告)日：2002-02-19

申请号：US09392391

申请日：1999-09-09

申请人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

发明人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218234

CPC分类号： H01L21/823857 ,  H01L21/823814

摘要： A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

摘要翻译： 提供了一种新的方法，由此使用一个处理顺序创建用于HV CMOS器件和LV CMOS器件的LDD区域。 用于高电压和低电压器件的栅电极都在硅衬底的表面上产生。 高压LDD（HVLDD）与HV CMOS栅电极自对准，对HV和LV CMOS器件进行栅极退火。 低压LDD（LVLDD）与LV CMOS栅电极自对准。 在CMOS器件的栅电极完成之后，形成栅极间隔物，源极/漏极注入和CMOS器件所需的后端处理。

公开(公告)号：US06297098B1

公开(公告)日：2001-10-02

申请号：US09431236

申请日：1999-11-01

申请人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

发明人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/26586

摘要： A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

摘要翻译： 公开了一种用于在闪速存储器应用中用于非易失性存储器和DDD（双掺杂漏极）的高压器件中形成LDD（轻掺杂漏极）的方法。 高压器件通过以倾斜角度使用两个连续的离子注入形成，其提供了接合点附近的掺杂分布的改进的灰度级，并且在更高的电压下提高了结点击穿。 层叠闪存单元中的双掺杂漏极也通过两次注入形成，但是以最佳倾角形成，其中第一次注入被轻掺杂，而第二次重掺杂。 由此产生的DDD提供更快的编程速度，减少编程电流，增加读取电流和减少闪存单元中的漏极干扰。

公开(公告)号：US6001687A

公开(公告)日：1999-12-14

申请号：US283849

申请日：1999-04-01

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8239

CPC分类号： H01L27/11521

摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.

摘要翻译： 当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。 通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。 之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。 当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

公开(公告)号：US06251744B1

公开(公告)日：2001-06-26

申请号：US09356870

申请日：1999-07-19

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

摘要翻译： 在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。 在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。 去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。 牺牲氧化物层沉积在半导体衬底的表面上。 在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

公开(公告)号：US06130168A

公开(公告)日：2000-10-10

申请号：US349844

申请日：1999-07-08

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/32 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/302

CPC分类号： H01L27/11526 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/954

摘要： A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.

摘要翻译： 描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。 提供半导体衬底，其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。 沉积在衬底表面上的隧道氧化物层上的多晶硅层。 去除多晶硅和隧道氧化物层，除了在存储单元区域中。 沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。 在高电压区域中去除ONO层。 衬底在高压区域被氧化以形成厚的栅极氧化物层。 此后，在低电压区域中去除ONO层，并且衬底被氧化以形成薄的栅极氧化物层。 第二多晶硅层沉积在存储区域中的ONO层上，在低电压区域的薄栅极氧化物层上方，以及高电压区域中的厚栅极氧化物层上方。 将存储单元区域中的第二多晶硅层，ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。 将第二多晶硅层图案化以在低电压区域中形成低压晶体管，并在高电压区域形成高压晶体管。

公开(公告)号：US6127227A

公开(公告)日：2000-10-03

申请号：US236491

申请日：1999-01-25

申请人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L29/511

摘要： A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.

摘要翻译： 公开了一种形成闪存单元的方法，其中采用氮气处理或植入。 引入浮栅的多晶硅的上层的氮有助于形成包含氮 - 氧 - 硅的异常薄的层。 在生长氧化物 - 氮化物 - 氧化物的底部氧化物层（ONO）的同时，在浮动栅极和闪存单元的控制栅极之间形成栅极层，形成N-O-Si层。 第一多晶硅层中的氮提供对底部氧化物的厚度的控制，同时抑制浮动栅极中的逐渐栅极氧化（GGO）效应。 现在通过N-O-Si层增强的ONO复合材料提供增强的隔间电介质，因此提供具有更精确的耦合比和更好性能的闪存单元。

公开(公告)号：US6153494A

公开(公告)日：2000-11-28

申请号：US310257

申请日：1999-05-12

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

摘要翻译： 提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。 这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕 填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源 本发明的闪存单元。 还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

公开(公告)号：US6037223A

公开(公告)日：2000-03-14

申请号：US177342

申请日：1998-10-23

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A process for fabricating a flash memory cell, featuring self-aligned contact structures, overlying and contacting, self-aligned source, and self-aligned drain regions, located between stack gate structures, has been developed. The stack gate structures, located on an underlying silicon dioxide, tunnel oxide layer, are comprised of: a capping insulator shape; a polysilicon control gate shape; an inter-polysilicon dielectric shape; and a polysilicon floating gate shape. The use of self-aligned contact structures, and self-aligned source regions, allows increased cell densities to be achieved.

摘要翻译： 已经开发了一种用于制造闪存单元的方法，其特征在于位于堆叠栅极结构之间的自对准接触结构，覆盖和接触自对准源极和自对准漏极区。 位于下面的二氧化硅隧道氧化物层上的堆叠栅极结构包括：封盖绝缘体形状; 多晶硅控制门形状; 多晶硅间介质形状; 和多晶硅浮栅形状。 使用自对准接触结构和自对准的源区域可以实现提高的细胞密度。

公开(公告)号：US6133096A

公开(公告)日：2000-10-17

申请号：US208917

申请日：1998-12-10

申请人： Hung-Der Su ,  Jong Chen ,  Chrong-Jung Lin ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jong Chen ,  Chrong-Jung Lin ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534

摘要： A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.

摘要翻译： 已经开发了在半导体衬底的第二区域上将闪存单元的制造在半导体衬底的第一区域上与制造水银外围器件进行集成的工艺。 闪存单元具有位于层叠栅极结构之间的SAC接触结构，接触下层的源/漏区。 堆叠栅极结构由覆盖多晶硅浮栅形状的介电层上的多晶硅控制栅极形状构成。 通过使用位于多晶硅栅极结构的顶表面上的金属硅化物层以及相邻的重掺杂源极/漏极区域来增加外围器件的性能。