公开(公告)号：US6087232A

公开(公告)日：2000-07-11

申请号：US135645

申请日：1998-08-18

申请人： Jong Dae Kim ,  Sang Ki Kim ,  Jin Gun Koo ,  Kee Soo Nam

发明人： Jong Dae Kim ,  Sang Ki Kim ,  Jin Gun Koo ,  Kee Soo Nam

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has been improved by using a new tapered p top layer on the surface of the drift region of the transistor, thereby decreasing the length of the drift region. Another advantage of the current invention is that the breakdown voltage similar with the on-resistance can be improved by using a reproducible tapered TEOS oxide by use of a multi-layer structure and low temperature annealing process. This is due to the reducing of the current path and impurity segregation in the drift region by using the tapered TEOS oxide instead of LOCOS filed oxide.

摘要翻译： 根据制造双RESURF（减少的SURface Field）LDMOS（侧向扩散金属氧化物半导体）晶体管的方法，通过在漂移区的表面上使用新的锥形p顶层，改善了双RESURF LDMOS晶体管的导通电阻 晶体管，从而减小漂移区的长度。 本发明的另一个优点是可以通过使用多层结构和低温退火工艺使用可再现的锥形TEOS氧化物来改善与导通电阻相似的击穿电压。 这是由于通过使用锥形TEOS氧化物而不是LOCOS氧化物来减少漂移区中的电流路径和杂质偏析。

公开(公告)号：US06534365B2

公开(公告)日：2003-03-18

申请号：US09726910

申请日：2000-11-29

申请人： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

发明人： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

摘要翻译： 使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。 此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

公开(公告)号：US06852597B2

公开(公告)日：2005-02-08

申请号：US10071127

申请日：2002-02-08

申请人： Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

发明人： Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/7802

摘要： A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC分类号： H03L500

CPC分类号： H03K19/0016

摘要： The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

摘要翻译： 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US06855581B2

公开(公告)日：2005-02-15

申请号：US10153975

申请日：2002-05-23

申请人： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

发明人： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

摘要翻译： 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

公开(公告)号：US09494543B2

公开(公告)日：2016-11-15

申请号：US13620546

申请日：2012-09-14

申请人： Seung Eon Moon ,  Nak Jin Choi ,  Hyung Kun Lee ,  Jae Woo Lee ,  Woo Seok Yang ,  Jong Dae Kim

发明人： Seung Eon Moon ,  Nak Jin Choi ,  Hyung Kun Lee ,  Jae Woo Lee ,  Woo Seok Yang ,  Jong Dae Kim

IPC分类号： G01N27/407 ,  G01N27/18 ,  G01N33/00

CPC分类号： G01N27/18 ,  G01N33/004

摘要： Disclosed is an electrochemical gas sensor using micro electro mechanical systems (MEMS). The MEMS electrochemical gas sensor includes: a substrate a lower central region of which is etched by a predetermined thickness; a first insulation film formed on the substrate; a heat emitting resistance body formed on the first insulation film; a second insulation film formed on the heat emitting resistance body; a reference electrode formed in an upper central region of the second insulation film; a solid electrolyte formed on the reference electrode; and a detection electrode formed on the solid electrolyte.

摘要翻译： 公开了一种使用微机电系统（MEMS）的电化学气体传感器。 MEMS电化学气体传感器包括：其下部中心区域被预定厚度蚀刻的衬底; 形成在所述基板上的第一绝缘膜; 形成在第一绝缘膜上的发热电阻体; 形成在所述发热电阻体上的第二绝缘膜; 参考电极，其形成在所述第二绝缘膜的上中央区域中; 形成在参比电极上的固体电解质; 和形成在固体电解质上的检测电极。

公开(公告)号：US09391462B2

公开(公告)日：2016-07-12

申请号：US13596618

申请日：2012-08-28

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Se Wan Heo ,  Ji Min Oh ,  Min Ki Kim ,  Jong Kee Kwon

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Se Wan Heo ,  Ji Min Oh ,  Min Ki Kim ,  Jong Kee Kwon

IPC分类号： H01F27/42 ,  H02J5/00 ,  H02J7/00

CPC分类号： H02J50/00 ,  H02J5/005 ,  H02J7/0063 ,  H02J7/025

摘要： Disclosed is an energy storage system provided with a wired and wireless energy transfer function. The energy storage system includes: an energy input unit to which energy generated from a plurality of energy sources is input; an energy input control unit for selecting one energy source from among the plurality of energy sources, and transferring energy of the selected energy source through operation in a wired operation mode or a wireless operation mode; a wireless energy transmitting/receiving unit for wirelessly transmitting/receiving the energy of the selected energy source during the operation in the wireless operation mode of the energy input control unit; an energy storage/control unit for storing the energy of the selected energy source; an energy output unit for consuming the energy stored in the energy storage/control unit; and an energy output control unit for distributing the energy stored in the energy storage/control unit to the energy output unit.

摘要翻译： 公开了一种具有有线和无线能量传递功能的能量存储系统。 能量存储系统包括：输入从多个能量源产生的能量的能量输入单元; 能量输入控制单元，用于从所述多个能量源中选择一个能量源，并且通过在有线操作模式或无线操作模式中的操作来传送所选择的能量源的能量; 无线能量发送/接收单元，用于在能量输入控制单元的无线操作模式下的操作期间，无线地发送/接收所选择的能量源的能量; 用于存储所选能量源的能量的能量存储/控制单元; 用于消耗存储在能量存储/控制单元中的能量的能量输出单元; 以及能量输出控制单元，用于将存储在能量存储/控制单元中的能量分配给能量输出单元。

公开(公告)号：US08873776B2

公开(公告)日：2014-10-28

申请号：US13289225

申请日：2011-11-04

申请人： Hye-Jin Kim ,  Woo Seok Yang ,  Jong Dae Kim

发明人： Hye-Jin Kim ,  Woo Seok Yang ,  Jong Dae Kim

IPC分类号： H04R25/00

CPC分类号： H04R17/005 ,  H04R2201/003 ,  H04R2307/025 ,  H04R2499/15

摘要： Disclosed is a piezoelectric speaker including: a piezoelectric layer that converts electrical signals into oscillation and outputs sound; an electrode that is formed on a top or a bottom of the piezoelectric layer to apply the electrical signals to the piezoelectric layer; an acoustic diaphragm that is made of a hetero material including a first acoustic diaphragm and a second acoustic diaphragm and is attached to the bottom of the piezoelectric layer on which the electrode is formed; and a frame attached in a form enclosing a side of the acoustic diaphragm.

摘要翻译： 公开了一种压电扬声器，包括：将电信号转换为振荡并输出声音的压电层; 形成在压电层的顶部或底部上以将电信号施加到压电层的电极; 由包括第一声膜和第二声膜的异质材料制成并附着在其上形成有电极的压电层的底部的声膜; 以及以包围隔膜的一侧的形式附接的框架。

公开(公告)号：US08731059B2

公开(公告)日：2014-05-20

申请号：US12105745

申请日：2008-04-18

申请人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Hoon Kim

发明人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Hoon Kim

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N7/26 ,  H04N7/50 ,  H04N7/36

CPC分类号： H04N19/00521 ,  H04N19/102 ,  H04N19/122 ,  H04N19/134 ,  H04N19/436 ,  H04N19/57 ,  H04N19/61 ,  H04N19/86

摘要： An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

摘要翻译： 提出了一种计算能够相对于多个当前帧宏块同时计算SAD值的可变块的运动估计的绝对差（SAD）的装置。 该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算在多个串行当前帧宏块中提供的至少一个像素的SAD值，包括电流 帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，并且将数据发送到在PE阵列单元中提供的每个PE，以及用于对提供在本地存储器中的数据进行命令的控制器 对应于至少一个像素，其中PE阵列单元中提供的每个PE执行计算。

公开(公告)号：US08503765B2

公开(公告)日：2013-08-06

申请号：US13636998

申请日：2011-04-08

申请人： Dae Sic Woo ,  Byoung Ki Jeon ,  A Ran Kim ,  Hong Woo Lee ,  Jong Dae Kim ,  Won Suk Chung

发明人： Dae Sic Woo ,  Byoung Ki Jeon ,  A Ran Kim ,  Hong Woo Lee ,  Jong Dae Kim ,  Won Suk Chung

IPC分类号： G06K9/00

CPC分类号： G06T5/005 ,  H04N13/111 ,  H04N13/128

摘要： An embodiment of the present invention relates to a method and apparatus for correcting errors in stereo images. The apparatus for correcting errors in stereo images according to an embodiment of the present invention comprises: a space histogram generation unit generating space histogram information using the depth map information on the input image data; a peak frequency generation unit generating a peak frequency using the 2D image data of the input image data; an object analysis unit determining the error in each frame of the input image data on the basis of the space histogram and peak frequency; a depth map error correction unit correcting the depth map information to reduce the error; and a rendering processing unit generating left and right eye images, which are stereo images, by using the corrected depth map information.

摘要翻译： 本发明的实施例涉及用于校正立体图像中的错误的方法和装置。 根据本发明的实施例的用于校正立体图像中的误差的装置包括：空间直方图生成单元，使用关于输入图像数据的深度图信息生成空间直方图信息; 峰值频率生成单元，使用输入图像数据的2D图像数据生成峰值频率; 对象分析单元，基于空间直方图和峰值频率来确定输入图像数据的每帧中的误差; 深度图错误校正单元，校正深度图信息以减少误差; 以及通过使用校正的深度图信息来生成左眼图像和右眼图像的再现处理单元，其是立体图像。