公开(公告)号：US20080106922A1

公开(公告)日：2008-05-08

申请号：US11735635

申请日：2007-04-16

申请人： Joon-Min Park ,  Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Joon-Min Park ,  Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C5/06 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/76

摘要： A semiconductor memory device and a layout structure of word line contacts, in which the semiconductor memory device includes an active region, a plurality of memory cells, and word line contacts. The active region is disposed in a first direction as a length direction on a semiconductor substrate and is used as a word line. The plurality of memory cells are disposed in the first direction on the active region and are each constructed of one variable resistance device and one diode device. In the word line contacts, at least one each is disposed between respective units, wherein each unit is constructed of predetermined numbers of memory cells on the active region. A bridge effect, such as a short-circuit between adjacent word lines, can be prevented or substantially reduced.

摘要翻译： 半导体存储器件和字线触点的布局结构，其中半导体存储器件包括有源区，多个存储单元和字线触点。 有源区域沿着半导体衬底上的长度方向的第一方向设置，并用作字线。 多个存储单元在有源区域上沿第一方向设置，并且分别由一个可变电阻器件和一个二极管器件构成。 在字线触点中，每个单元之间至少设置一个，其中每个单元由有源区上的预定数量的存储单元构成。 可以防止或显着减少诸如相邻字线之间的短路的桥接效应。

公开(公告)号：US20090316474A1

公开(公告)日：2009-12-24

申请号：US12457319

申请日：2009-06-08

申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

IPC分类号： G11C11/00 ,  G11C29/00

CPC分类号： G11C29/808 ,  G11C13/0004

摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

公开(公告)号：US08023319B2

公开(公告)日：2011-09-20

申请号：US12457319

申请日：2009-06-08

申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

IPC分类号： G11C11/00

CPC分类号： G11C29/808 ,  G11C13/0004

摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

公开(公告)号：US20100131708A1

公开(公告)日：2010-05-27

申请号：US12292896

申请日：2008-11-28

申请人： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

发明人： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

IPC分类号： G06F12/00

CPC分类号： G11C13/0069 ,  G11C15/046 ,  G11C2013/0076

摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.

摘要翻译： 在一个实施例中，半导体器件包括非易失性存储器单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器，以及写入地址缓冲器，被配置为存储与存储的每个数据相关联的写入地址 在写缓冲区。 输出电路被配置为选择性地输出从非易失性存储器阵列读取的数据和来自写入缓冲器的数据之一。 旁路控制电路被配置为基于输入读取地址是否匹配存储在写入地址缓冲器中的有效写入地址来控制输出电路。 如果所存储的写入地址与输入写入地址相匹配，则无效单元被配置为使存储在写入地址缓冲器中的地址无效。

公开(公告)号：US07573758B2

公开(公告)日：2009-08-11

申请号：US11853955

申请日：2007-09-12

申请人： Joon-Min Park ,  Du-Eung Kim

发明人： Joon-Min Park ,  Du-Eung Kim

IPC分类号： G11C7/22

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/0069 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C2213/79

摘要： A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation on the data, and a program loop control unit storing program verification result for the test cell at each program loop during test operation and generating the program pulse according to the program verification result to control the start of the program loop during normal operation.

摘要翻译： 公开了PRAM和编程方法。 PRAM包括存储单元阵列，其包括测试单元，施加编程脉冲并向存储单元阵列提供编程电流的写入驱动器，读取在存储单元阵列中编程的数据并执行程序验证操作的读出放大和验证电路 以及程序循环控制单元，其在测试操作期间在每个程序循环处存储测试单元的程序验证结果，并根据程序验证结果产生编程脉冲，以控制正常操作期间程序循环的开始。

公开(公告)号：US08174878B2

公开(公告)日：2012-05-08

申请号：US13053471

申请日：2011-03-22

申请人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

发明人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

摘要翻译： 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元 外部提供的升压电压。

公开(公告)号：US07936619B2

公开(公告)日：2011-05-03

申请号：US12339204

申请日：2008-12-19

申请人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

发明人： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC分类号： G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

摘要翻译： 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元 使用外部提供的升压电压。

公开(公告)号：US08248860B2

公开(公告)日：2012-08-21

申请号：US12659840

申请日：2010-03-23

申请人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

发明人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

IPC分类号： G11C16/04

CPC分类号： G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

摘要翻译： 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

公开(公告)号：US07843715B2

公开(公告)日：2010-11-30

申请号：US12015624

申请日：2008-01-17

申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/72

摘要： A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The twin cell includes a main unit cell connected to a main bit line and a word line, and a sub unit cell connected to a sub bit line and the word line. Also, the main unit cell includes a first variable resistor and a first diode, and the sub unit cell includes a second variable resistor and a second diode.

摘要翻译： 提供了电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法。 电阻半导体存储器件的存储单元包括双胞胎，其中双胞胎存储表示一位数据的数据值。 双胞胎单元包括连接到主位线和字线的主单元，以及连接到子位线和字线的子单元。 此外，主单元包括第一可变电阻器和第一二极管，并且子单元电池包括第二可变电阻器和第二二极管。

公开(公告)号：US07808811B2

公开(公告)日：2010-10-05

申请号：US12020237

申请日：2008-01-25

申请人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

发明人： Joon-Min Park ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.

摘要翻译： 提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。 在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线 层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由 预定数量的子字线。 可以实现足够高集成度的有效的字线解码。