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    Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
    1.
    发明授权
    Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same 有权
    具有多层侧壁间隔结构的非易失性半导体存储器件及其制造方法

    公开(公告)号：US06555865B2

    公开(公告)日：2003-04-29

    申请号：US09902820

    申请日：2001-07-10

    申请人： Joon-Sung Lee ,  Woon-Kyung Lee

    发明人： Joon-Sung Lee ,  Woon-Kyung Lee

    IPC分类号： H01L2976

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/792

    摘要： The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A multi-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. With the present invention, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack of nonvolatile memory cell can be protected with the first nitride layer from mobile ions. Also, etching damage to source/drain regions or field regions can be reduced.

    摘要翻译： 本发明提供一种具有高可靠性的新型侧壁间隔结构的非易失性存储器件。 用于非易失性存储器件的栅极堆叠结构包括半导体衬底，形成在半导体衬底上的栅叠层。 栅极堆叠具有侧壁和顶部表面。 在栅叠层的侧壁上形成多层侧壁间隔结构。 多层侧壁间隔结构包括依次堆叠的第一氧化物层，第一氮化物层，第二氧化物层和第二氮化物层。 利用本发明，即使在形成接触孔期间第二氮化物层被穿孔或损坏，非易失性存储单元的栅极堆叠的侧壁可以被移动离子的第一氮化物层保护。 此外，可以减少对源极/漏极区域或场区域的蚀刻损伤。

    METALLIC LAMINATE AND MANUFACTURING METHOD OF CORE SUBSTRATE USING THE SAME
    2.
    发明申请
    METALLIC LAMINATE AND MANUFACTURING METHOD OF CORE SUBSTRATE USING THE SAME 审中-公开
    金属层压板和使用其的芯基板的制造方法

    公开(公告)号：US20110126970A1

    公开(公告)日：2011-06-02

    申请号：US12773325

    申请日：2010-05-04

    申请人： Sang-Youp LEE ,  Joung-Gul Ryu ,  Dong-Sun Kim ,  Jae-Hoon Choi ,  In-Ho Seo ,  Joon-Sung Lee

    发明人： Sang-Youp LEE ,  Joung-Gul Ryu ,  Dong-Sun Kim ,  Jae-Hoon Choi ,  In-Ho Seo ,  Joon-Sung Lee

    IPC分类号： B32B38/10 ,  B32B15/04 ,  B32B15/00

    CPC分类号： B32B15/20 ,  B32B37/185 ,  B32B2305/342 ,  B32B2311/12 ,  B32B2457/00 ,  Y10T428/12535

    摘要： A metallic laminate and a method of manufacturing a core substrate using the same are disclosed. In accordance with an embodiment of the present invention, the metallic laminate includes an insulation material, a carrier layer, which is stacked on both surfaces of the insulation layer and in which the carrier layer is a metal, and a first metal foil, which is stacked on one surface of the carrier layer. By symmetrically forming two core substrates on either surface above and below the insulation material, each process of forming the core substrate can be performed at the same time in the shape of a pair of facing core substrates, thereby increasing the productivity by twice. The remaining insulation material having the carrier layer stacked thereon can be used as a base substrate that is used to manufacture a printed circuit board, thus preventing unnecessary waste of the insulation material.

    摘要翻译： 公开了一种金属层压体和使用其的芯基板的制造方法。 根据本发明的实施例，金属层压体包括绝缘材料，层叠在绝缘层的两个表面上并且载体层是金属的载体层和第一金属箔 层叠在载体层的一个表面上。 通过在绝缘材料上方和下方的任一表面对称地形成两个芯基板，形成芯基板的每个工艺可以同时以一对相对的芯基板的形状进行，从而将生产率提高两倍。 具有堆叠在其上的载体层的剩余绝缘材料可以用作用于制造印刷电路板的基底，从而防止绝缘材料的不必要的浪费。

    Method for isolating semiconductor devices
    3.
    发明授权
    Method for isolating semiconductor devices 失效
    隔离半导体器件的方法

    公开(公告)号：US6060399A

    公开(公告)日：2000-05-09

    申请号：US923108

    申请日：1997-09-04

    申请人： Young-Gwan Kim ,  Joon-Sung Lee

    发明人： Young-Gwan Kim ,  Joon-Sung Lee

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/30

    CPC分类号： H01L21/76232

    摘要： A semiconductor device isolation method includes sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, exposing a predetermined portion of the surface of the semiconductor substrate, forming a third insulating on the exposed surface of the semiconductor substrate and the second insulating film, forming sidewall spacers composed of the third insulating film at the sidewall surfaces of the first and second insulating films, forming a trench by performing an etching by a predetermined depth using the sidewall spacers as a mask, removing the sidewall spacers, filling a high density plasma chemical vapor deposition (HDP CVD) oxide in the trench, and removing the first and second insulating films.

    摘要翻译： 半导体器件隔离方法包括：在半导体衬底上依次形成第一绝缘膜和第二绝缘膜，暴露半导体衬底的表面的预定部分，在半导体衬底的暴露表面上形成第三绝缘体，将第二绝缘层 在所述第一和第二绝缘膜的侧壁形成由所述第三绝缘膜构成的侧壁隔离物，通过使用所述侧壁间隔物作为掩模，通过以预定深度进行蚀刻而形成沟槽，除去所述侧壁间隔物，填充高 密度等离子体化学气相沉积（HDP CVD）氧化物，以及去除第一和第二绝缘膜。

    PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：US20110127073A1

    公开(公告)日：2011-06-02

    申请号：US12755825

    申请日：2010-04-07

    申请人： Joung-Gul Ryu ,  Sang-Youp Lee ,  Dong-Sun Kim ,  Jae-Hoon Choi ,  In-Ho Seo ,  Joon-Sung Lee

    发明人： Joung-Gul Ryu ,  Sang-Youp Lee ,  Dong-Sun Kim ,  Jae-Hoon Choi ,  In-Ho Seo ,  Joon-Sung Lee

    IPC分类号： H05K1/09 ,  H05K3/46

    CPC分类号： H05K3/4608

    摘要： A printed circuit board and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the printed circuit board includes a metal core having Invar layers formed on either surface of a copper layer, an insulation layer, which is formed on one surface of the metal core, and a circuit pattern, which is coupled to one surface of the insulation layer. Thus, the printed circuit board can improve thermal conductivity and deformation resistance against warpage.

    摘要翻译： 公开了印刷电路板及其制造方法。 根据本发明的实施例，印刷电路板包括在铜层的任一表面上形成的具有殷钢层的金属芯，形成在金属芯的一个表面上的绝缘层和电路图案， 其耦合到绝缘层的一个表面。 因此，印刷电路板可以提高导热性和抗翘曲变形性。

    CORE SUBSTRATE AND METHOD OF MANUFACTURING CORE SUBSTRATE
    6.
    发明申请
    CORE SUBSTRATE AND METHOD OF MANUFACTURING CORE SUBSTRATE 审中-公开
    核心基板及制造核心基板的方法

    公开(公告)号：US20110123772A1

    公开(公告)日：2011-05-26

    申请号：US12755857

    申请日：2010-04-07

    申请人： Sang-Youp Lee ,  Joung-Gul Ryu ,  Dong-Sun Kim ,  Jae-Hoon Choi ,  In-Ho Seo ,  Joon-Sung Lee

    发明人： Sang-Youp Lee ,  Joung-Gul Ryu ,  Dong-Sun Kim ,  Jae-Hoon Choi ,  In-Ho Seo ,  Joon-Sung Lee

    IPC分类号： B32B3/28 ,  B44C3/02

    CPC分类号： B32B7/12 ,  B32B3/266 ,  B32B15/08 ,  B32B27/06 ,  B32B27/34 ,  Y10T156/1039 ,  Y10T428/24479

    摘要： A core substrate and a method of manufacturing the core substrate are disclosed. In accordance with an embodiment of the present invention, the core substrate includes an adhesive resin layer having a mineral filler added therein, a metal sheet, which is patterned and embedded in the adhesive resin layer, and an insulation layer, which is stacked on both surfaces of the adhesive resin layer. Since a through-hole is formed to correspond to the number of via holes in accordance with a higher density of a printed circuit board, no conventional land is required to be formed, thereby reducing the defect of eccentricity.

    摘要翻译： 公开了芯基板和芯基板的制造方法。 根据本发明的实施例，芯基板包括其中添加有矿物填料的粘合树脂层，被图案化并嵌入粘合树脂层中的金属片和层叠在两者上的绝缘层 粘合树脂层的表面。 由于根据印刷电路板的较高密度形成通孔以对应于通孔的数量，所以不需要形成常规的焊盘，从而减少偏心的缺陷。