公开(公告)号：US09997462B2

公开(公告)日：2018-06-12

申请号：US15581782

申请日：2017-04-28

申请人： Jooyeon Ha ,  Jeonggil Lee ,  Dohyung Kim ,  Keun Lee ,  HyunSeok Lim ,  Hauk Han

发明人： Jooyeon Ha ,  Jeonggil Lee ,  Dohyung Kim ,  Keun Lee ,  HyunSeok Lim ,  Hauk Han

IPC分类号： H01L27/115 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/788 ,  H01L27/11578

CPC分类号： H01L23/535 ,  H01L23/53266 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A memory device includes a vertical string of nonvolatile memory cells on a substrate, along with a ground selection transistor extending between the vertical string of nonvolatile memory cells and the substrate. The ground selection transistor can have a current carrying terminal electrically coupled to a channel region of a nonvolatile memory cell in the vertical string of nonvolatile memory cells. The ground selection transistor includes a gate electrode associated with a ground selection line of the memory device. This gate electrode includes: (i) a mask pattern, (ii) a barrier metal layer of a first material extending opposite a sidewall of the mask pattern and (iii) a metal pattern of a second material different from the first material extending between at least a portion of the barrier metal layer and the mask pattern.

公开(公告)号：US10079245B2

公开(公告)日：2018-09-18

申请号：US15249090

申请日：2016-08-26

申请人： Hauk Han ,  Je-Hyeon Park ,  Kihyun Yoon ,  Changwon Lee ,  HyunSeok Lim ,  Jooyeon Ha

发明人： Hauk Han ,  Je-Hyeon Park ,  Kihyun Yoon ,  Changwon Lee ,  HyunSeok Lim ,  Jooyeon Ha

IPC分类号： H01L23/52 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L21/76847 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

公开(公告)号：US08415674B2

公开(公告)日：2013-04-09

申请号：US12874865

申请日：2010-09-02

申请人： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

发明人： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

IPC分类号： H01L29/10

CPC分类号： H01L27/11578 ,  H01L21/28556 ,  H01L21/76879 ,  H01L23/485 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/145 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

摘要翻译： 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。

公开(公告)号：US20110049646A1

公开(公告)日：2011-03-03

申请号：US12874865

申请日：2010-09-02

申请人： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

发明人： Tai-Soo Lim ,  HyunSeok Lim ,  Shin-Jae Kang ,  Kyung-Tae Jang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/28556 ,  H01L21/76879 ,  H01L23/485 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/145 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

摘要翻译： 形成半导体器件的方法包括在半导体结构上形成绝缘层，在绝缘层中形成开口，该开口具有由绝缘层的一侧限定的侧壁，在开口中形成第一金属层，至少部分地 通过对第一金属层进行湿蚀刻工艺，并且在蚀刻的第一金属层上选择性地形成第二金属层，使开口的侧壁暴露。 第一金属层的平均粒径小于第二金属层的平均粒径。 还公开了相关的半导体器件。

公开(公告)号：US20100129947A1

公开(公告)日：2010-05-27

申请号：US12591393

申请日：2009-11-18

申请人： Hyun-Suk Lee ,  Tai-Soo Lim ,  HyunSeok Lim ,  Insun Park ,  Jaehyoung Choi

发明人： Hyun-Suk Lee ,  Tai-Soo Lim ,  HyunSeok Lim ,  Insun Park ,  Jaehyoung Choi

IPC分类号： H01L45/00 ,  H01L21/00

CPC分类号： H01L45/141 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

摘要： In the method of fabricating the variable-resistance memory device, a substrate including a conductive region is provided, and a preliminary lower electrode is formed on the conductive region. A lower electrode is formed by oxidizing an upper portion of the preliminary lower electrode. A phase-change material layer is formed on the lower electrode.

摘要翻译： 在制造可变电阻存储器件的方法中，提供了包括导电区域的衬底，并且在导电区域上形成预备下电极。 通过氧化预备下电极的上部形成下电极。 在下电极上形成相变材料层。