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21 条记录 (耗时 0.027 秒)

    Divergence feedback in a linear fiber optic analog transmission system and method
    4.
    发明授权
    Divergence feedback in a linear fiber optic analog transmission system and method 失效
    线性光纤模拟传输系统和方法的发散反馈

    公开(公告)号：US5535039A

    公开(公告)日：1996-07-09

    申请号：US355168

    申请日：1994-12-08

    申请人： Donald K. Belcher ,  David M. Thomas

    发明人： Donald K. Belcher ,  David M. Thomas

    IPC分类号： H04B10/155 ,  H04B10/04 ,  H04B10/12

    CPC分类号： H04B10/58 ,  H04B10/5057 ,  H04B2210/254

    摘要： A method and apparatus for improving the linearity of an analog signal in a fiber optic transmission system in which copies of the analog signal are provided to a remote receiver and to a feedback receiver, and in which the copy to the feedback receiver is attenuated so that the signal received at the feedback receiver is substantially similar to the signal received at the remoter receiver. An amplifier subtractively combines the signal from the feedback receiver and the analog signal to thereby provide a signal that pre-compensates for non-linearities that would be encountered by a transmission through the system. The feedback receiver and the remote receiver are substantially similar in operation so that the feedback loop substantially duplicates the environment of the transmission.

    摘要翻译： 一种用于改善光纤传输系统中模拟信号的线性度的方法和装置，其中模拟信号的副本被提供给远程接收机和反馈接收机，并且其中向反馈接收机的复制被衰减，使得 在反馈接收机处接收的信号基本上类似于在远距离接收机处接收的信号。 放大器将来自反馈接收器的信号和模拟信号相减，从而提供预先补偿通过系统的传输将遇到的非线性的信号。 反馈接收器和远程接收器在操作中基本相似，使得反馈回路基本上复制了传输的环境。

    Dynamic error compensation in track-and-hold circuits
    6.
    发明授权
    Dynamic error compensation in track-and-hold circuits 有权
    跟踪和保持电路中的动态误差补偿

    公开(公告)号：US06281717B1

    公开(公告)日：2001-08-28

    申请号：US09457628

    申请日：1999-12-08

    申请人： David M. Thomas ,  Richard J. Reay

    发明人： David M. Thomas ,  Richard J. Reay

    IPC分类号： G11C2702

    CPC分类号： G11C27/026 ,  G11C27/024 ,  H03K17/063

    摘要： Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

    摘要翻译： 提供电路和方法，其补偿由诸如轨道和保持电路之类的电路中与电容器串联耦合的开关上的电压降引起的动态误差。 在这样的电路中，电容器应该提供与耦合到开关的信号相同的电压，但不是因为开关电压降。 该开关可以是例如MOSFET或更具体的CMOS器件。 通过测量开关两端的电压降来补偿动态误差，然后将测得的电压降有效地加到由电容器提供的电压上。

    Cell to word buffer
    8.
    发明授权
    Cell to word buffer 失效
    单元到单词缓冲区

    公开(公告)号：US4568941A

    公开(公告)日：1986-02-04

    申请号：US393334

    申请日：1982-06-29

    申请人： David M. Thomas ,  Leonard J. Tubb ,  Jean C. Castonguay

    发明人： David M. Thomas ,  Leonard J. Tubb ,  Jean C. Castonguay

    IPC分类号： G01S7/298 ,  G11C7/00 ,  G11C7/10 ,  G01S7/04 ,  H04N7/01

    CPC分类号： G11C7/1006 ,  G01S7/298 ,  G11C7/00

    摘要： Disclosed is a cell to word buffer for use in a digital TV display radar system in which radar pulse returns are digitized by an analog to digital converter to form pixel data, polar coordinates of the pulse returns are converted to their equivalent X, Y cartesian coordinates by a coordinate converter and the pixel data are stored in an X, Y refresh memory array in accordance with their X, Y coordinates for use in refreshing a TV display. The cell to word buffer allows large offsets in high resolution radar scan converters. The cell to word buffer memory means is located intermediate the coordinate converter and refresh memory for temporarily storing, for each Y location, a plurality of groups of adjacent pixel data and their associated X addresses and for transferring each group of pixel data to its appropriate location in the refresh memory when each group in the buffer memory is filled with pixel data. Further buffer registers of the first in, first out type may be provided intermediate the buffer memory and the refresh memory for smoothing the rate of data transfers therebetween. Also, peak detection means may be provided to avoid loss of pixel data for radar samples near the origin.

    摘要翻译： 公开了一种用于数字电视显示雷达系统中的单元到字缓冲器，其中雷达脉冲返回由模数转换器数字化以形成像素数据，脉冲返回的极坐标被转换为等效的X，Y笛卡尔坐标 通过坐标转换器，并且像素数据根据它们的X，Y坐标存储在X，Y刷新存储器阵列中，用于刷新TV显示。 单元到字缓冲器允许高分辨率雷达扫描转换器中的大偏移。 单元到字缓冲存储器装置位于坐标转换器和刷新存储器之间，用于为每个Y位置临时存储多组相邻像素数据及其相关联的X地址，并将每组像素数据传送到其适当的位置 在刷新存储器中，缓冲存储器中的每个组都填充有像素数据。 可以在缓冲存储器和刷新存储器之间提供第一进入类型的另外的缓冲寄存器，用于平滑其间的数据传输速率。 此外，可以提供峰值检测装置以避免在原点附近的雷达样本的像素数据丢失。

    System and methods to improve the performance of semiconductor based sampling system
    9.
    发明授权
    System and methods to improve the performance of semiconductor based sampling system 有权
    提高半导体采样系统性能的系统和方法

    公开(公告)号：US08482442B2

    公开(公告)日：2013-07-09

    申请号：US13155922

    申请日：2011-06-08

    申请人： David M. Thomas

    发明人： David M. Thomas

    IPC分类号： H03M1/00

    CPC分类号： G11C7/02 ,  G11C27/024

    摘要： Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

    摘要翻译： 提供了提高电子采样系统性能的电路和方法。 至少部分地通过补偿所遇到的输入信号变化以减少或最小化与通过采样开关的采样信号相关联的信号失真，在采样状态期间与采样半导体开关相关联的阻抗保持基本恒定。

    Two-step subranging analog to digital converter
    10.
    发明授权
    Two-step subranging analog to digital converter 失效
    两步子模拟数字转换器

    公开(公告)号：US5070332A

    公开(公告)日：1991-12-03

    申请号：US671219

    申请日：1991-03-18

    申请人： Roy S. Kaller ,  David M. Thomas

    发明人： Roy S. Kaller ,  David M. Thomas

    IPC分类号： H03M1/14 ,  H03M1/06 ,  H03M1/08 ,  H03M1/16 ,  H03M1/36 ,  H03M1/74

    CPC分类号： H03M1/0619 ,  H03M1/089 ,  H03M1/146 ,  H03M1/162 ,  H03M1/365 ,  H03M1/742

    摘要： A subranging analog-to-digital converter (ADC) that comprises a biasing architecture including a single string of transistor current sources used to generate the reference digital-to-analog converter (DAC) bit currents, the low-resolution flash ADC reference ladder voltage, and the ADC bipolar offset voltage. The reference DAC resistors, low resolution voltage reference ladder resistors, error amplifier gain set resistors, and the bipolar offset resistors are all constructed from the same material and using the same physical construction, so that they match with high precision and track over process and temperature. In one embodiment, the low-resolution flash ADC is itself implemented as a two-step parallel subranging ADC, comprising a most-significant-bit reference ladder and a least-significant-bit reference ladder, and includes an internal flash DAC whose bit currents are also provided by the same single string of transistor current sources. In addition, a shunt resistor across the least-significant-bit reference ladder of the low-resolution flash ADC makes it possible to tie it in series directly to its most-significant-bit reference ladder using the same resistor material, thus providing inherent tracking of the reference voltages of the two ladders. Finally, a bias current compensation resistor network is provided on the input side of the flash ADC comparators to cancel input bias current errors.

    摘要翻译： 一种包含模拟 - 数字转换器（ADC），包括偏置架构，包括用于产生参考数/模转换器（DAC）位电流的单串晶体管电流源，低分辨率闪存ADC参考梯形电压 ，和ADC双极性偏移电压。 参考DAC电阻，低分辨率电压参考梯形电阻，误差放大器增益设置电阻和双极性失调电阻都由相同的材料构成，并使用相同的物理结构，使其与高精度跟踪过程和温度匹配 。 在一个实施例中，低分辨率闪存ADC本身被实现为两级并行子阵列ADC，其包括最高有效位参考梯形图和最低有效位参考梯形图，并且包括内部闪存DAC，其位电流 也由相同的单串晶体管电流源提供。 此外，低分辨率闪存ADC的最低有效位参考梯形图之间的分流电阻可以使用相同的电阻材料直接与其最高有效位参考梯级串联，从而提供固有的跟踪 的两个梯子的参考电压。 最后，在闪存ADC比较器的输入侧提供偏置电流补偿电阻网络，以消除输入偏置电流误差。