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1.发明申请Semiconductor memory device and method of operating a semiconductor memory device 审中-公开半导体存储器件和操作半导体存储器件的方法公开(公告)号：US20070231991A1
公开(公告)日：2007-10-04
申请号：US11396398
申请日：2006-03-31
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/14 , G11C16/16
摘要： A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge carriers from the channel region to move into the charge-trapping layer and to cause a second current of a second kind of charge carriers from the gate electrode to move into the charge-trapping layer, until the value of the second current is at least half the amount of the first current value.
摘要翻译： 半导体存储器件包括沟道区，与沟道区相邻的栅电极以及沟道区和栅电极之间的电荷俘获层。 在栅极电极和沟道区域之间施加电压，使来自沟道区域的第一种电荷载流子的第一电流移动到电荷俘获层中，并引起第二种载流子的第二电流 栅电极移动到电荷捕获层中，直到第二电流的值至少为第一电流值的一半。
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公开(公告)号：US20070082446A1
公开(公告)日：2007-04-12
申请号：US11246908
申请日：2005-10-07
IPC分类号： H01L21/336 , H01L21/76 , H01L21/302 , H01L21/461
CPC分类号： H01L27/115 , H01L21/76897 , H01L27/11568
摘要： A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.
摘要翻译： 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。
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3.发明授权Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US07365382B2
公开(公告)日：2008-04-29
申请号：US11067983
申请日：2005-02-28
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。
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4.发明申请Semiconductor memory having charge trapping memory cells and fabrication method thereof 有权具有电荷捕获存储单元的半导体存储器及其制造方法公开(公告)号：US20060192266A1
公开(公告)日：2006-08-31
申请号：US11067983
申请日：2005-02-28
IPC分类号： H01L29/00
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42336 , H01L29/7923
摘要： A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.
摘要翻译： 一种具有电荷捕获存储单元的半导体存储器，其中存储晶体管的每个沟道区域的电流方向相对于相关字线横向延伸，位线被布置在字线的顶侧，并且以某种方式 存在与源极 - 漏极区电气绝缘的导电局部互连件，其在字线之间的间隔中以部分布置并以与后者的电绝缘方式并且连接到位线的方式布置，其中栅极电极 布置在至少部分地形成在存储器基板中的沟槽中。
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公开(公告)号：US07368350B2
公开(公告)日：2008-05-06
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译： 公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。 提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。 在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。 另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。 接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。
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公开(公告)号：US20070141799A1
公开(公告)日：2007-06-21
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译： 公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。 提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。 在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。 另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。 接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。
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7.发明申请Method of production of a semiconductor memory device and semiconductor memory device 审中-公开半导体存储器件和半导体存储器件的制造方法公开(公告)号：US20080081424A1
公开(公告)日：2008-04-03
申请号：US11541458
申请日：2006-09-29
申请人： Josef Willer , Karl-Heinz Kuesters
发明人： Josef Willer , Karl-Heinz Kuesters
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A layer of electrically conductive material is applied above a carrier surface. Gate electrodes are formed above a first area of the carrier surface from the electrically conductive material. An implantation of a dopant that is provided for source/drain regions is performed in the first area. The implant is annealed, and an auxiliary layer of a dielectric material is applied to planarize the surface. The first area is covered with a mask, and a further implantation of a dopant provided for source/drain regions is performed in a second area of the carrier surface provided for a memory cell array. The implant is annealed, and the memory cells are formed in the second area. The semiconductor memory device may comprise a selectively deposited electrically conductive material on the gate electrodes of the periphery and on buried bitlines of the memory cell array.
摘要翻译： 在载体表面上施加一层导电材料。 栅电极形成在载体表面的与导电材料的第一区域之上。 在第一区域中执行为源极/漏极区域提供的掺杂剂的注入。 将植入物退火，并且施加介电材料的辅助层以使表面平坦化。 第一区域被掩模覆盖，并且在为存储单元阵列提供的载体表面的第二区域中执行为源/漏区提供的掺杂剂的进一步注入。 将植入物退火，并且在第二区域中形成存储器单元。 半导体存储器件可以包括在周边的栅电极和存储单元阵列的掩埋位线上的选择性沉积的导电材料。
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公开(公告)号：US20070042553A1
公开(公告)日：2007-02-22
申请号：US11506159
申请日：2006-08-17
IPC分类号： H01L21/8236
CPC分类号： H01L27/115 , H01L27/11568
摘要： A storage layer sequence (20) and gate electrodes (34) are arranged on a substrate (10). The gate electrodes (34) may be fabricated in a gate electrode layer (22) made of electrically conductively doped polysilicon. Apart from an optional barrier layer (45), the word lines are solely formed from a material having a low resistivity, preferably from a metal layer (46). Word line spacers (52) are arranged on sidewalls for the purpose of electrical insulation and as a barrier against outdiffusion of metal atoms.
摘要翻译： 存储层序列（20）和栅电极（34）布置在基板（10）上。 栅极（34）可以制造在由导电掺杂多晶硅制成的栅电极层（22）中。 除了可选的阻挡层（45）之外，字线仅由具有低电阻率的材料形成，优选地由金属层（46）形成。 字线间隔件（52）布置在侧壁上用于电绝缘并且作为防止金属原子扩散的屏障。
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9.发明授权Three-dimensional one-dimensional cell arrangement for dynamic semiconductor memories and method for the manufacture of a bit line contact 失效用于动态半导体存储器的三维一维单元布置和用于制造位线接触的方法
公开(公告)号：US5025295A
公开(公告)日：1991-06-18
申请号：US464685
申请日：1990-01-16
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A three-dimensional, one transistor cell arrangement for dynamic semiconductor memories utilizing a trench capacitor in the substrate, and provided with a switching field effect transistor including an insulated gate electrode connected to the source/drain zone, the bit line contact for the connection of the switching transistor being arranged to be self-adjusted on the drain region in the semiconductor substrate, and overlapping the gate electrode with insulating layers on all sides. It also overlaps the neighboring field oxide region. The insulation layer laying beneath the bit line and over the gate level is a triple layer composed of silicon oxide/silicon nitride/silicon oxide, and in the through hole etching which is carried out by specific etching steps, there exists a self-adjusted overlapping contact. By eliminating the imprecision caused by the lithography, the space requirement of a memory cell can be reduced by about 20%. The invention is particularly utilized in the manufacture of 4 megabit DRAMs.
摘要翻译： 一种用于在衬底中利用沟槽电容器的动态半导体存储器的三维一晶体管单元布置，并且设置有包括连接到源极/漏极区的绝缘栅电极的开关场效应晶体管，用于连接 所述开关晶体管被布置为在所述半导体衬底的漏极区域上自调节，并且在所述侧面上与所述栅电极重叠。 它也与相邻的场氧化物区域重叠。 位于位线下方和栅极层以下的绝缘层是由氧化硅/氮化硅/氧化硅构成的三层，并且在通过特定蚀刻步骤进行的通孔蚀刻中，存在自调整重叠 联系。 通过消除由光刻引起的不精确度，存储单元的空间需求可以减少大约20％。 本发明特别用于制造4兆比特DRAM。
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10.发明授权Work roll with improved support and lubricating system for an hydraulically supported roll 失效工作辊具有改进的液压支撑辊的支撑和润滑系统
公开(公告)号：US4962577A
公开(公告)日：1990-10-16
申请号：US494806
申请日：1990-03-14
申请人： Klaus Kubik , Karl-Heinz Kuesters
发明人： Klaus Kubik , Karl-Heinz Kuesters
CPC分类号： F16C13/026 , D21G1/022 , D21G1/0226 , F16C13/02
摘要： In a roll having a hollow roll through which a stationary cross piece extends, a bearing housing is provided for a bearing which engages an axial extension of the hollow roll. The extension has a smaller outer diameter than the outer diameter of the hollow roll. The bearing is located in the bearing housing between the outside circumference of the extension and the inside circumference of the bearing housing. The bearing housing has lubricant feed and discharge passages separate from means for hydraulically supporting the hollow roll. The bearing housing has a bore which fits over the end of the cross piece without play thereby forming a support distance.
摘要翻译： 在具有中空辊的卷筒中，固定横档通过该中空辊延伸，为与中空辊的轴向延伸部接合的轴承提供轴承壳体。 延伸部的外径比中空辊的外径小。 轴承位于轴承外壳的延伸部外周和轴承座的内周之间。 轴承壳体具有与用于液压支撑中空辊的装置分离的润滑剂进料和排出通道。 轴承壳体具有孔，该孔在十字架的端部上配合而不起作用，从而形成支撑距离。
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