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公开(公告)号：US20090217010A1
公开(公告)日：2009-08-27
申请号：US12035961
申请日：2008-02-22
IPC分类号： G06F9/00
CPC分类号： G06F11/3471 , G06F11/348
摘要： In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.
摘要翻译： 响应于确定事件发生，信息被存储在集成电路的跟踪缓冲器中。 当跟踪缓冲器已满时，CPU停止执行指令，以允许在集成电路设备的外部接口访问跟踪缓冲区信息。 随着跟踪缓冲区的填充，CPU会持续停止，以便检索写入跟踪缓冲区的所有信息。
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公开(公告)号：US08312253B2
公开(公告)日：2012-11-13
申请号：US12035961
申请日：2008-02-22
IPC分类号： G06F9/00
CPC分类号： G06F11/3471 , G06F11/348
摘要： In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.
摘要翻译： 响应于确定事件发生，信息被存储在集成电路的跟踪缓冲器中。 当跟踪缓冲器已满时，CPU停止执行指令，以允许在集成电路设备的外部接口访问跟踪缓冲区信息。 随着跟踪缓冲区的填充，CPU会持续停止，以便检索写入跟踪缓冲区的所有信息。
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公开(公告)号：US20140259149A1
公开(公告)日：2014-09-11
申请号：US13789387
申请日：2013-03-07
IPC分类号： G06F21/70
CPC分类号： G06F21/85 , G06F12/1458 , G06F21/74
摘要： A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
摘要翻译： 可以对可以被配置为在特定安全模式（例如具有一个或多个信道的直接存储器访问（DMA））中作为主机的设备的存储位置进行编程，以指示当被配置为 作为主设备运行。
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4.发明申请公开(公告)号：US20090217298A1
公开(公告)日：2009-08-27
申请号：US12035967
申请日：2008-02-22
IPC分类号： G06F13/00
摘要： A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
摘要翻译： 处理器响应于异常事件开始异常处理。 处理器异常处理在异常处理期间停止，以方便调试。 异常事件可以是复位异常事件或中断异常事件。 数据处理器的正常异常处理可以在调试后恢复，或者可以中止数据处理器的异常处理，以允许数据处理器恢复正常执行指令。 可以将异常事件选择性地视为中断或复位。
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公开(公告)号：US09489316B2
公开(公告)日：2016-11-08
申请号：US13842006
申请日：2013-03-15
CPC分类号： G06F12/1425 , G06F9/30181 , G06F9/324 , G06F9/34 , G06F9/3814 , G06F9/3824 , G06F9/3861 , G06F2212/202
摘要： Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
摘要翻译： 允许从指定为只执行存储器类型的存储器空间访问数据操作数的访问请求，以响应于确定使用特定类型的寻址模式生成操作数访问请求。
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公开(公告)号：US08417924B2
公开(公告)日：2013-04-09
申请号：US12035969
申请日：2008-02-22
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30181
摘要： A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
摘要翻译： 处理器响应于异常事件开始异常处理。 处理器异常处理在异常处理期间停止，以方便调试。 异常事件可以是复位异常事件或中断异常事件。 数据处理器的正常异常处理可以在调试后恢复，或者可以中止数据处理器的异常处理，以允许数据处理器恢复正常执行指令。 可以将异常事件选择性地视为中断或复位。
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公开(公告)号：US07433803B2
公开(公告)日：2008-10-07
申请号：US11116672
申请日：2005-04-27
IPC分类号： G06F11/30
CPC分类号： G06F11/348 , G06F11/3476
摘要： A system and method for performance monitoring in processors is provided. The system and method evaluates the performance of the processor by counting selected events during one or more defined periods. The performance monitor provides improved performance characterization by providing highly-configurable start-stop control over the event counting.
摘要翻译： 提供了一种用于处理器中性能监控的系统和方法。 系统和方法通过在一个或多个定义的周期内计数所选事件来评估处理器的性能。 性能监视器通过为事件计数提供高度可配置的启动 - 停止控制来提供改进的性能表征。
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公开(公告)号：US06766433B2
公开(公告)日：2004-07-20
申请号：US09957780
申请日：2001-09-21
IPC分类号： G06F1210
摘要： A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers (70-72) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.
摘要翻译： 系统（10）响应于包含在输入地址内的控制信息来实现用户可编程寻址模式。 存储在多个用户编程的地址置换控制寄存器（70-72）中的编码控制信息用于确定使用什么位值来替换输入地址的预定位以选择性地创建相应的置换地址。 由于不需要修改处理器的流水线，因此可以使用通用处理器或专用处理器来对用户定义和实现各种置换寻址模式。
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公开(公告)号：US4928225A
公开(公告)日：1990-05-22
申请号：US240747
申请日：1988-09-02
CPC分类号： G06F12/0866 , G06F12/0831 , G06F12/0848 , G06F12/1054 , G06F12/0835
摘要： A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.
摘要翻译： 多处理系统包括高速缓存一致性技术，其确保对一行数据的每次访问是该行的最新的副本，而不将高速缓存一致性状态位存储在全局存储器中以及对其的任何引用。 操作数缓存包括直接在一对一的基础上将物理地址位的范围映射到操作数高速缓冲存储器的第一部分中的第一目录。 关联目录乘法将物理地址超出范围的映射映射到操作数高速缓存存储部分的第二部分。 要在时间共享的基础上执行的所有用户程序的堆栈帧被存储在第一部分中，因此避免了由于堆栈操作导致的高速缓存未命中。 各种类别的指令的指令高速缓存存储一组标识每个指令的指令类别的状态位。 当发生上下文切换时，由于由于上下文切换而导致指令高速缓存清除，所以仅在最近将来可能使用的类别的指令被清除减少延迟。 页面映射的I / O缓存结构由大量I / O通道接口，将单个I / O缓存视为独占缓冲区。 由于维护高速缓存一致性，操作数高速缓存未命中，指令高速缓存未命中，I / O高速缓存未命中以及维护高速缓存一致性引起的系统运行延迟大大降低。
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公开(公告)号：US10073797B2
公开(公告)日：2018-09-11
申请号：US12035967
申请日：2008-02-22
摘要： A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
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