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23 条记录 (耗时 0.027 秒)

    Method and apparatus for increasing the recording time of a digital video tape recorder
    3.
    发明授权
    Method and apparatus for increasing the recording time of a digital video tape recorder 失效
    用于增加数字录像机的记录时间的方法和装置

    公开(公告)号：US5493456A

    公开(公告)日：1996-02-20

    申请号：US385390

    申请日：1995-02-07

    申请人： Joseph E. Augenbraun ,  Jill M. Boyce ,  Larry A. Pearlstein

    发明人： Joseph E. Augenbraun ,  Jill M. Boyce ,  Larry A. Pearlstein

    IPC分类号： G11B5/008 ,  G11B5/53 ,  G11B15/02 ,  G11B15/087 ,  G11B15/12 ,  G11B15/18 ,  G11B15/467 ,  G11B15/52 ,  H04N7/26 ,  H04N9/804 ,  H04N21/236 ,  H04N21/4147 ,  H04N21/434 ,  G11B5/09 ,  G11B15/14

    CPC分类号： H04N19/00 ,  G11B15/125 ,  G11B15/1875 ,  G11B15/4673 ,  G11B15/52 ,  G11B5/0086 ,  G11B5/00865 ,  G11B5/534 ,  H04N19/184 ,  H04N19/37 ,  H04N19/40 ,  H04N19/80 ,  H04N21/236 ,  H04N21/4147 ,  H04N21/434 ,  H04N9/8042 ,  G11B15/02 ,  G11B15/087 ,  H04N19/30

    摘要： Method for increasing the recording time of a digital video tape recorder ("VTR") and for supporting multiple normal play modes of digital VTR operation, e.g., a standard play mode of operation and one or more long play modes of operation. To achieve long play mode operation data reduction is performed on a received full rate video data stream to generate a reduced rate video data stream. Data reduction is performed using data prioritization and selection, requantization of full rate data stream, and/or by selecting data to be included in the reduced rate data stream as a function of what portion of a video frame the data represents. The reduced rate data stream is generated to be compliant with the data format of the full rate data stream. During long play mode recording operation the data in the reduced rate data stream is recorded on a tape at the same tape data density as used during standard mode VTR operation. In accordance with each of the recording methods of the present invention the rotational rate of the digital VTRs headwheel is the same for both standard and long play modes of VTR operation. In addition, the present invention is directed to several methods of reading data from a tape at a reduced data rate.

    摘要翻译： 用于增加数字录像机（“VTR”）的记录时间并用于支持数字VTR操作的多种正常播放模式的方法，例如标准播放操作模式和一种或多种长时间播放操作模式。 为了实现长播放模式操作，对接收到的全速率视频数据流执行数据缩减以产生降低速率的视频数据流。 使用数据优先化和选择，全速率数据流的重新排序和/或通过选择要包括在降低速率数据流中的数据作为数据表示的视频帧的部分的函数来执行数据缩减。 生成降低速率数据流以符合全速率数据流的数据格式。 在长播放模式记录操作期间，降低速率数据流中的数据以与在标准模式VTR操作期间使用的磁带数据密度相同地记录在磁带上。 根据本发明的每种记录方法，数字VTR前轮的旋转速率对于VTR操作的标准和长时间播放模式是相同的。 此外，本发明涉及以减小的数据速率从磁带读取数据的几种方法。

    Method and apparatus for improved video display of progressively refreshed coded video
    5.
    发明授权
    Method and apparatus for improved video display of progressively refreshed coded video 失效
    用于改进逐渐刷新的编码视频的视频显示的方法和装置

    公开(公告)号：US5568200A

    公开(公告)日：1996-10-22

    申请号：US477787

    申请日：1995-06-07

    申请人： Larry A. Pearlstein ,  Joseph E. Augenbraun ,  Frank A. Lane

    发明人： Larry A. Pearlstein ,  Joseph E. Augenbraun ,  Frank A. Lane

    IPC分类号： G06T9/00 ,  H04N5/44 ,  H04N7/26 ,  H04N7/50 ,  H04N7/52 ,  H04N7/64

    CPC分类号： H04N7/52 ,  H04N19/174 ,  H04N19/61 ,  H04N5/4401 ,  H04N19/107

    摘要： A method and apparatus for controlling the display of progressively refreshed decoded compressed image representative data is disclosed. Subframes of intracoded video signals, and subframes of intercoded video signals based on the intracoded video signals of successive video frames are used to construct a reference video frame. Refresh descriptor data is provided indicating the number of video frames necessary for acquiring intracoded video signals to form the reference video frame. The display of video frames is inhibited based on the refresh descriptor data until a suitable video frame of intracoded video signals and intercoded video signals based thereon is constructed. In another embodiment of the invention, at least one array of memory elements is provided for storing data corresponding to the subframes of a video frame. Each subframe of a video frame corresponds to one element of the memory array. Data indications are stored to mark as "clean" or initialized the regions of subframes having intracoded video signals and subframes having intercoded video signals based on the intracoded video signals. Substitute video signals are provided to conceal portions of respective video frames not marked as initialized, thereby provide a more pleasing picture to the viewer.

    摘要翻译： 公开了一种用于控制逐渐刷新的解码压缩图像代表数据的显示的方法和装置。 使用内部编码的视频信号的子帧，以及基于连续视频帧的内部编码的视频信号的帧间视频信号的子帧来构造参考视频帧。 提供刷新描述符数据，指示获取内部编码视频信号以形成参考视频帧所需的视频帧的数量。 基于刷新描述符数据禁止视频帧的显示，直到构成了基于内部编码的视频信号和基于帧间视频信号的适当的视频帧。 在本发明的另一个实施例中，提供至少一个存储元件阵列用于存储对应于视频帧的子帧的数据。 视频帧的每个子帧对应于存储器阵列的一个元素。 数据指示被存储以标记为“干净”或基于内部编码的视频信号来初始化具有内部编码视频信号的子帧的区域和具有相互间的视频信号的子帧。 提供替代视频信号以隐藏未被标记为初始化的各个视频帧的部分，从而向观看者提供更令人愉悦的画面。

    Method and apparatus for transmitting and using picture descriptive information in a frame rate conversion processor
    6.
    发明授权
    Method and apparatus for transmitting and using picture descriptive information in a frame rate conversion processor 有权
    用于在帧速率转换处理器中发送和使用图像描述信息的方法和装置

    公开(公告)号：US09204086B2

    公开(公告)日：2015-12-01

    申请号：US12174738

    申请日：2008-07-17

    申请人： Samir N. Hulyalkar ,  Larry A. Pearlstein

    发明人： Samir N. Hulyalkar ,  Larry A. Pearlstein

    IPC分类号： H04N7/173 ,  H04N7/01 ,  H04N21/431 ,  H04N21/434 ,  H04N21/4402 ,  H04N5/445 ,  H04N5/45

    CPC分类号： H04N7/013 ,  H04N5/45 ,  H04N7/0112 ,  H04N7/0132 ,  H04N7/0135 ,  H04N21/4316 ,  H04N21/4348 ,  H04N21/440281

    摘要： A method and apparatus of frame rate conversion where descriptive information relating to an input video signal is transmitted to the frame rate converter along with the input signal. The descriptive information is used to interpolate frames, allowing the interpolator to make pixel analysis using the descriptive information relating to the original signal. The descriptive information is derived by a compositor/scaler and is transmitted to the frame rate converter with the composited/scaled signal. There may be multiple input signals that are composited to make a final composited video output such as a picture-in-picture display. The information may be transmitted in-band with the video signal received by the frame rate converter. Alternatively, the descriptive information may be transmitted in a separate stream in a side-band manner. In another embodiment, the descriptive information may be transmitted to the frame rate converter separate from the video input source as commands or packets.

    摘要翻译： 一种帧率转换的方法和装置，其中与输入视频信号相关的描述信息与输入信号一起发送到帧速率转换器。 描述信息用于内插帧，允许内插器使用与原始信号相关的描述信息进行像素分析。 描述信息由合成器/缩放器导出，并通过合成/缩放信号传输到帧速率转换器。 可以合成多个输入信号以进行最终的合成视频输出，例如画中画显示。 该信息可以与由帧速率转换器接收的视频信号一起带内传输。 或者，描述性信息可以在单独的流中以侧带方式发送。 在另一个实施例中，描述信息可以作为命令或分组被发送到与视频输入源分离的帧速率转换器。

    SIMD processor with register addressing, buffer stall and methods
    7.
    发明授权
    SIMD processor with register addressing, buffer stall and methods 有权
    具有寄存器寻址，缓冲区失速和方法的SIMD处理器

    公开(公告)号：US07434024B2

    公开(公告)日：2008-10-07

    申请号：US10929992

    申请日：2004-08-30

    申请人： Richard J. Selvaggi ,  Larry A. Pearlstein

    发明人： Richard J. Selvaggi ,  Larry A. Pearlstein

    IPC分类号： G06F9/26 ,  G06F9/34 ,  G06F12/02

    CPC分类号： G06F9/345 ,  G06F9/30101 ,  G06F9/3555

    摘要： A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

    摘要翻译： 公开了一种用于灵活计算有效操作数源和目的地存储器地址的单指令多数据（SIMD）处理器，包括多个寻址寄存器组。 两个或多个地址生成器使用寄存器集计算有效地址。 每个寄存器组包括一个指针寄存器和一个比例寄存器。 地址生成器从所选择的寄存器组的指针寄存器和比例寄存器形成有效地址; 和一个偏移。 例如，有效存储器地址可以通过将比例值乘以偏移值并将指针与刻度值相乘而乘以偏移值来形成。

    SIMD processor and addressing method
    8.
    发明申请
    SIMD processor and addressing method 有权
    SIMD处理器和寻址方法

    公开(公告)号：US20090125702A1

    公开(公告)日：2009-05-14

    申请号：US12231336

    申请日：2008-08-29

    申请人： Richard J. Selvaggi ,  Larry A. Pearlstein

    发明人： Richard J. Selvaggi ,  Larry A. Pearlstein

    IPC分类号： G06F9/345

    CPC分类号： G06F9/345 ,  G06F9/30101 ,  G06F9/3555

    摘要： A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

    摘要翻译： 公开了一种用于灵活计算有效操作数源和目的地存储器地址的单指令多数据（SIMD）处理器，包括多个寻址寄存器组。 两个或多个地址生成器使用寄存器集计算有效地址。 每个寄存器组包括一个指针寄存器和一个刻度寄存器。 地址生成器从所选择的寄存器组的指针寄存器和比例寄存器形成有效地址; 和一个偏移。 例如，有效存储器地址可以通过将比例值乘以偏移值并将指针与刻度值相乘而乘以偏移值来形成。

    METHODS AND APPARATUS FOR PROCESSING VARIABLE LENGTH CODED DATA
    9.
    发明申请
    METHODS AND APPARATUS FOR PROCESSING VARIABLE LENGTH CODED DATA 失效
    用于处理可变长度编码数据的方法和装置

    公开(公告)号：US20080231482A1

    公开(公告)日：2008-09-25

    申请号：US12133489

    申请日：2008-06-05

    申请人： Larry A. Pearlstein ,  Richard Sita ,  Richard J. Selvaggi

    发明人： Larry A. Pearlstein ,  Richard Sita ,  Richard J. Selvaggi

    IPC分类号： H03M7/40

    CPC分类号： H03M7/40

    摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

    摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。

    Methods and apparatus for processing variable length coded data
    10.
    发明授权
    Methods and apparatus for processing variable length coded data 失效
    用于处理可变长度编码数据的方法和装置

    公开(公告)号：US07385534B2

    公开(公告)日：2008-06-10

    申请号：US11538336

    申请日：2006-10-03

    申请人： Larry A. Pearlstein ,  Richard Sita ,  Richard J. Selvaggi

    发明人： Larry A. Pearlstein ,  Richard Sita ,  Richard J. Selvaggi

    IPC分类号： H03M7/00

    CPC分类号： H03M7/40

    摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

    摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。