公开(公告)号：US20120286377A1

公开(公告)日：2012-11-15

申请号：US13103193

申请日：2011-05-09

申请人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Michael A. Guillorn ,  Fei Liu ,  Conal E. Murray

发明人： Josephine B. Chang ,  Sebastian U. Engelmann ,  Michael A. Guillorn ,  Fei Liu ,  Conal E. Murray

IPC分类号： H01L29/84 ,  H01L21/3105 ,  H01L29/06

CPC分类号： H01L29/84 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0307 ,  H01L29/0673

摘要： Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.

摘要翻译： 改进的纳米机电系统设备及其制造的结构及系统和技术。 在一个实施例中，结构包括分别通过第一和第二绝缘支撑点从第一和第二锚定点分离的下面的基底。 第一和第二锚定点通过梁连接。 第一和第二沉积区域分别覆盖在第一和第二锚定点上，并且第一和第二沉积区域分别在第一和第二锚定点上施加压缩。 第一和第二锚固点上的压缩在梁上产生相反的力，使梁受到拉伸应力。 第一和第二沉积区域适当地呈现具有随其厚度变化的可实现最大值的内部拉伸应力，使得施加在梁上的拉伸应力至少部分地取决于第一和第二沉积区域的厚度。

公开(公告)号：US08198174B2

公开(公告)日：2012-06-12

申请号：US12536176

申请日：2009-08-05

申请人： Louis L. Hsu ,  Brian L. Ji ,  Fei Liu ,  Conal E. Murray

发明人： Louis L. Hsu ,  Brian L. Ji ,  Fei Liu ,  Conal E. Murray

IPC分类号： H01L21/44

CPC分类号： H01L23/467 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.

摘要翻译： 提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合 在其接合界面处的垂直堆叠的晶片的晶片。 此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过 一个或多个开口以从芯片堆叠结构移除热量。

公开(公告)号：US20110031633A1

公开(公告)日：2011-02-10

申请号：US12536176

申请日：2009-08-05

申请人： Louis L. Hsu ,  Brain L. Ji ,  Fei Liu ,  Conal E. Murray

发明人： Louis L. Hsu ,  Brain L. Ji ,  Fei Liu ,  Conal E. Murray

IPC分类号： H01L23/532 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L23/467 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.

摘要翻译： 提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合 在其接合界面处的垂直堆叠的晶片的晶片。 此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过 一个或多个开口以从芯片堆叠结构移除热量。

公开(公告)号：US20120181508A1

公开(公告)日：2012-07-19

申请号：US13009280

申请日：2011-01-19

申请人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

发明人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0688 ,  H01L21/28506 ,  H01L21/8221 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/78684

摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

摘要翻译： 三维集成电路包括硅衬底，设置在衬底上的第一源极区域，设置在衬底上的第一漏极区域，设置在衬底上的第一栅极堆叠部分，设置在第一源极区域上的第一电介质层， 第一漏极区域，第一栅极堆叠部分和衬底，形成在第一电介质层上的第二电介质层，设置在第二电介质层上的第二源极区域，设置在第二电介质层上的第二漏极区域，以及第二漏极区域 栅极堆叠部分设置在第二介电层上，第二栅极堆叠部分包括石墨烯层。

公开(公告)号：US08748871B2

公开(公告)日：2014-06-10

申请号：US13352737

申请日：2012-01-18

申请人： Phaedon Avouris ,  Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu ,  Yanqing Wu ,  Wenjuan Zhu

发明人： Phaedon Avouris ,  Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu ,  Yanqing Wu ,  Wenjuan Zhu

IPC分类号： H01L27/088

CPC分类号： H01L27/0688 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/78684

摘要： A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

摘要翻译： 三维集成电路包括半导体器件，形成在半导体器件上的绝缘体，形成在绝缘体中的互连以及形成在绝缘体上的石墨烯器件。

公开(公告)号：US08587067B2

公开(公告)日：2013-11-19

申请号：US13559941

申请日：2012-07-27

申请人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

发明人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

IPC分类号： H01L27/088

CPC分类号： H01L27/0688 ,  H01L21/28506 ,  H01L21/8221 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/78684

摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

摘要翻译： 三维集成电路包括硅衬底，设置在衬底上的第一源极区域，设置在衬底上的第一漏极区域，设置在衬底上的第一栅极堆叠部分，设置在第一源极区域上的第一电介质层， 第一漏极区域，第一栅极堆叠部分和衬底，形成在第一电介质层上的第二电介质层，设置在第二电介质层上的第二源极区域，设置在第二电介质层上的第二漏极区域，以及第二漏极区域 栅极堆叠部分设置在第二介电层上，第二栅极堆叠部分包括石墨烯层。

公开(公告)号：US20120292702A1

公开(公告)日：2012-11-22

申请号：US13559941

申请日：2012-07-27

申请人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

发明人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

IPC分类号： H01L27/088 ,  B82Y99/00

CPC分类号： H01L27/0688 ,  H01L21/28506 ,  H01L21/8221 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/78684

摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

公开(公告)号：US08409957B2

公开(公告)日：2013-04-02

申请号：US13009280

申请日：2011-01-19

申请人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

发明人： Josephine B. Chang ,  Wilfried E. Haensch ,  Fei Liu ,  Zihong Liu

IPC分类号： H01L21/336

CPC分类号： H01L27/0688 ,  H01L21/28506 ,  H01L21/8221 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/78684

摘要： A three dimensional integrated circuit includes a silicon substrate, a first source region disposed on the substrate, a first drain region disposed on the substrate, a first gate stack portion disposed on the substrate, a first dielectric layer disposed on the first source region, the first drain region, the first gate stack portion, and the substrate, a second dielectric layer formed on the first dielectric layer, a second source region disposed on the second dielectric layer, a second drain region disposed on the second dielectric layer, and a second gate stack portion disposed on the second dielectric layer, the second gate stack portion including a graphene layer.

公开(公告)号：US08470628B2

公开(公告)日：2013-06-25

申请号：US13164126

申请日：2011-06-20

申请人： Michael A Guillorn ,  Eric A Joseph ,  Fei Liu ,  Zhen Zhang

发明人： Michael A Guillorn ,  Eric A Joseph ,  Fei Liu ,  Zhen Zhang

IPC分类号： H01L21/66

CPC分类号： B81C1/00666 ,  B81C1/00952 ,  H01H1/0094 ,  H01H2001/0078

摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction.

摘要翻译： 公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。 该方法包括提供设置在设置在硅衬底上的绝缘层上的硅层; 从所述绝缘层释放所述硅层的一部分，使得其至少部分地悬挂在所述绝缘层中的空腔上; 在至少所述硅层的释放部分的至少一个表面上沉积金属（例如Pt），并且使用热处理，使用沉积的金属至少完全硅化硅层的释放部分。 当整个Si元件被硅化时，该方法消除了对释放的Si元件的硅化物引起的应力。 此外，在形成完全硅化材料之后，也不使用常规的湿化学蚀刻，从而减少引起硅化物腐蚀和粘性增加的可能性。

公开(公告)号：US20130020183A1

公开(公告)日：2013-01-24

申请号：US13625294

申请日：2012-09-24

申请人： Michael A. Guillorn ,  Eric A. Joseph ,  Fei Liu ,  Zhen Zhang

发明人： Michael A. Guillorn ,  Eric A. Joseph ,  Fei Liu ,  Zhen Zhang

IPC分类号： H01H59/00

CPC分类号： B81C1/00666 ,  B81C1/00952 ,  H01H1/0094 ,  H01H2001/0078

摘要： A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material.

摘要翻译： 小型化机电开关包括具有触点的可移动部分，该触点构造成当开关被致动时使得两个静止点之间的电连接。 至少接触由完全硅化的材料组成。 一种结构包括形成在绝缘体层上的硅层和至少部分地形成在硅层内的微机电开关。 微机械开关具有导电结构，并且其中导电结构的至少电接触部分由完全硅化材料构成。