公开(公告)号：US20100008169A1

公开(公告)日：2010-01-14

申请号：US12585428

申请日：2009-09-15

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07911862B2

公开(公告)日：2011-03-22

申请号：US12585428

申请日：2009-09-15

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07609584B2

公开(公告)日：2009-10-27

申请号：US11594807

申请日：2006-11-09

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07580319B2

公开(公告)日：2009-08-25

申请号：US11715478

申请日：2007-03-08

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

IPC分类号： G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096

摘要： An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.

摘要翻译： 提供输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法。 示例性半导体存储器件可以包括被配置为基于外部时钟信号产生内部时钟信号的时钟缓冲器，被配置为对外部命令信号进行解码以产生写入命令信号的命令解码器和被配置为对 地址信号，以及基于内部时钟信号，写入命令信号和写入等待时间信号产生列地址信号和存储体地址信号。 示例性输入延迟控制电路可以包括主电路，其被配置为基于内部时钟信号，写命令信号和写等待时间信号来生成列控制信号和第一写地址控制信号，至少一列从属电路被配置为 在流水线模式下门控第一地址信号，以响应于列控制信号和第一写地址控制信号和第二写地址控制信号中的一个产生列地址信号，并且至少一个存储体从属电路被配置为选通第二地址信号 地址信号，以响应于列控制信号和第一和第二写地址控制信号中的至少一个来产生存储体地址信号。

公开(公告)号：US20070211556A1

公开(公告)日：2007-09-13

申请号：US11715478

申请日：2007-03-08

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim ,  Sung-Hoon Kim

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096

摘要： An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.

摘要翻译： 提供输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法。 示例性半导体存储器件可以包括被配置为基于外部时钟信号产生内部时钟信号的时钟缓冲器，被配置为对外部命令信号进行解码以产生写入命令信号的命令解码器和被配置为对 地址信号，以及基于内部时钟信号，写入命令信号和写入等待时间信号产生列地址信号和存储体地址信号。 示例性输入延迟控制电路可以包括主电路，其被配置为基于内部时钟信号，写命令信号和写等待时间信号来生成列控制信号和第一写地址控制信号，至少一列从属电路被配置为 在流水线模式下门控第一地址信号，以响应于列控制信号和第一写地址控制信号和第二写地址控制信号中的一个产生列地址信号，并且至少一个存储体从属电路被配置为选通第二地址信号 地址信号，以响应于列控制信号和第一和第二写地址控制信号中的至少一个来产生存储体地址信号。

公开(公告)号：US07388417B2

公开(公告)日：2008-06-17

申请号：US11519252

申请日：2006-09-12

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

IPC分类号： H03K17/62

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356156

摘要： An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

摘要翻译： 半导体存储器件的输出电路包括第一数据路径，第二数据路径和第三数据路径。 第一数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第二数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第三数据路径锁存第一节点的信号，并传送第一节点的信号以产生输出数据。 因此，包括输出电路的半导体存储器件可以使用将波形管线结构与完整管线结构组合在一起的伪流水线结构化电路以相对较高的频率工作。

公开(公告)号：US20070069788A1

公开(公告)日：2007-03-29

申请号：US11519252

申请日：2006-09-12

申请人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

发明人： Kyoung-Ho Kim ,  Seong-Jin Jang ,  Joung-Yeal Kim

IPC分类号： H03K3/00

CPC分类号： G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356156

摘要： An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

摘要翻译： 半导体存储器件的输出电路包括第一数据路径，第二数据路径和第三数据路径。 第一数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第二数据路径传送感测输出信号，并锁存感测输出信号以将感测输出信号输出到第一节点。 第三数据路径锁存第一节点的信号，并传送第一节点的信号以产生输出数据。 因此，包括输出电路的半导体存储器件可以使用将波形管线结构与完整管线结构组合在一起的伪流水线结构化电路以相对较高的频率工作。

公开(公告)号：US20110044121A1

公开(公告)日：2011-02-24

申请号：US12860484

申请日：2010-08-20

申请人： Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

发明人： Joung-Yeal Kim ,  Soo-Bong Chang ,  Seong-Jin Jang ,  Jin-Seok Kwak ,  Dong-Hak Shin

IPC分类号： G11C7/06

CPC分类号： G11C11/4094 ,  G11C11/4091 ,  G11C2207/005

摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.

摘要翻译： 半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器， 读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块 。

公开(公告)号：US20110205822A1

公开(公告)日：2011-08-25

申请号：US13006832

申请日：2011-01-14

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

IPC分类号： G11C7/06 ,  G01R19/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。

公开(公告)号：US08432762B2

公开(公告)日：2013-04-30

申请号：US13006832

申请日：2011-01-14

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。