公开(公告)号：US08856693B2

公开(公告)日：2014-10-07

申请号：US13606055

申请日：2012-09-07

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

IPC分类号： G06F17/50 ,  G03F7/00 ,  G03F1/38

CPC分类号： G03F1/38 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/00 ,  G03F7/0002

摘要： A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

摘要翻译： 一种用于设计光学掩模的方法和计算机系统，用于在基底上的光致抗蚀剂层中形成预模式开口，其中光致抗蚀剂层和预图案开口用自组装材料涂覆，所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括：从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

公开(公告)号：US08336003B2

公开(公告)日：2012-12-18

申请号：US12708570

申请日：2010-02-19

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

IPC分类号： G06F17/50

CPC分类号： G03F1/38 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/00 ,  G03F7/0002

摘要： A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

摘要翻译： 一种用于设计光学掩模的方法和计算机系统，用于在基底上的光致抗蚀剂层中形成预模式开口，其中光致抗蚀剂层和预图案开口用自组装材料涂覆，所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括：从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

公开(公告)号：US20110209106A1

公开(公告)日：2011-08-25

申请号：US12708570

申请日：2010-02-19

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

IPC分类号： G06F17/50

CPC分类号： G03F1/38 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/00 ,  G03F7/0002

摘要： A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

摘要翻译： 一种用于设计光学掩模的方法和计算机系统，用于在基底上的光致抗蚀剂层中形成预模式开口，其中光致抗蚀剂层和预图案开口用自组装材料涂覆，所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括：从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

公开(公告)号：US20120331428A1

公开(公告)日：2012-12-27

申请号：US13606055

申请日：2012-09-07

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Jed Walter Pitera ,  Charles Thomas Rettner ,  Daniel Paul Sanders ,  Da Yang

IPC分类号： G06F17/50

CPC分类号： G03F1/38 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/00 ,  G03F7/0002

摘要： A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

摘要翻译： 一种用于设计光学掩模的方法和计算机系统，用于在基底上的光致抗蚀剂层中形成预模式开口，其中光致抗蚀剂层和预图案开口用自组装材料涂覆，所述自组装材料经过定向自组装以形成定向自身 装配模式 所述方法包括：从目标设计形状生成掩模设计形状; 基于掩模设计形状产生子分辨率辅助特征设计形状; 使用计算机基于子分辨率辅助特征设计形状生成预绘图形状; 并且使用计算机来评估基于预图案形状的自组装材料的定向自组装图案是否在基板上的目标设计形状的尺寸和位置目标的指定范围内。

公开(公告)号：US08114306B2

公开(公告)日：2012-02-14

申请号：US12470760

申请日：2009-05-22

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders ,  Da Yang

IPC分类号： H01L21/31 ,  H01L21/469 ,  B32B3/00 ,  B05D3/00

CPC分类号： H01L21/76816 ,  B81B2203/0353 ,  B81B2207/07 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/31144 ,  Y10S438/947

摘要： Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes.

摘要翻译： 本文描述了涉及嵌段共聚物的自组装的方法，其中从具有目标CD（临界尺寸）的开口（在一个或多个衬底中）开始，以规则阵列或任意布置形成孔。 显着地，形成的孔的平均直径的百分比变化小于初始开口的平均直径的变化百分比。 形成的孔（或通孔）可以被转移到下面的基底中，然后这些孔可以用诸如金属导体的材料回填。 本发明的优选方面能够创建具有更紧的间距和更好的CD均匀性的通孔，即使在22nm以下的技术节点。

公开(公告)号：US20100297847A1

公开(公告)日：2010-11-25

申请号：US12470760

申请日：2009-05-22

申请人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders ,  Da Yang

发明人： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders ,  Da Yang

IPC分类号： H01L21/465

CPC分类号： H01L21/76816 ,  B81B2203/0353 ,  B81B2207/07 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/31144 ,  Y10S438/947

摘要： Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes.

摘要翻译： 本文描述了涉及嵌段共聚物的自组装的方法，其中从具有目标CD（临界尺寸）的开口（在一个或多个衬底中）开始，以规则阵列或任意布置形成孔。 显着地，形成的孔的平均直径的百分比变化小于初始开口的平均直径的变化百分比。 形成的孔（或通孔）可以被转移到下面的基底中，然后这些孔可以用诸如金属导体的材料回填。 本发明的优选方面能够创建具有更紧的间距和更好的CD均匀性的通孔，即使在22nm以下的技术节点处。

公开(公告)号：US08420492B2

公开(公告)日：2013-04-16

申请号：US13143591

申请日：2011-01-27

申请人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7845

摘要： The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.

摘要翻译： 本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。 本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

公开(公告)号：US08669160B2

公开(公告)日：2014-03-11

申请号：US13696308

申请日：2012-05-16

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu ,  Da Yang

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu ,  Da Yang

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor device is provided. The method comprises providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供半导体衬底; 在所述半导体衬底上形成虚拟栅极结构和围绕所述虚设栅极结构的间隔物; 使用所述虚拟栅极结构和所述间隔物作为掩模，在所述半导体衬底内的所述栅极结构的两侧上形成源极/漏极区域; 在所述半导体衬底的上表面上形成层间电介质层，所述层间电介质层的上表面与所述虚拟栅极结构的上表面齐平; 去除所述伪栅极结构的至少一部分，以形成由所述间隔物包围的沟槽; 使用层间电介质层和间隔物作为掩模对半导体衬底进行倾斜角度离子注入，以形成不对称的光晕注入区域; 在沟槽中依次形成栅介电层和金属栅极。

公开(公告)号：US20130309831A1

公开(公告)日：2013-11-21

申请号：US13696308

申请日：2012-05-16

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu ,  Da Yang

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu ,  Da Yang

IPC分类号： H01L29/66

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric Halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench. The present invention prevents the Halo implanted ions from entering into the source/drain regions, thus reducing the source/drain junction capacitance; and the asymmetric Halo implantation region can reduce the static power dissipation of the semiconductor device.

摘要翻译： 一种制造半导体器件的方法，包括：提供半导体衬底; 在所述半导体衬底上形成虚拟栅极结构和围绕所述虚设栅极结构的间隔物; 使用所述虚拟栅极结构和所述间隔物作为掩模，在所述半导体衬底内的所述栅极结构的两侧上形成源极/漏极区域; 在所述半导体衬底的上表面上形成层间电介质层，所述层间电介质层的上表面与所述虚拟栅极结构的上表面齐平; 去除所述伪栅极结构的至少一部分，以形成由所述间隔物包围的沟槽; 使用层间电介质层和间隔物作为掩模对半导体衬底进行倾斜角度离子注入，以形成不对称的光晕注入区域; 在沟槽中依次形成栅介电层和金属栅极。 本发明防止卤素注入的离子进入源极/漏极区域，从而减小源极/漏极结电容; 并且不对称光晕注入区域可以降低半导体器件的静态功耗。

公开(公告)号：US20120168829A1

公开(公告)日：2012-07-05

申请号：US13143591

申请日：2011-01-27

申请人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7845

摘要： The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.

摘要翻译： 本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。 本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。