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10 条记录 (耗时 0.072 秒)

    Method and apparatus for terminating direct memory access transfers from system memory to a video device
    4.
    发明授权
    Method and apparatus for terminating direct memory access transfers from system memory to a video device 有权
    用于终止从系统存储器传输到视频设备的直接存储器访问的方法和装置

    公开(公告)号：US06275242B1

    公开(公告)日：2001-08-14

    申请号：US09224657

    申请日：1998-12-31

    申请人： Nilesh V. Shah ,  Andrew E. Roedel ,  Cliff D. Hall

    发明人： Nilesh V. Shah ,  Andrew E. Roedel ,  Cliff D. Hall

    IPC分类号： G06F1316

    CPC分类号： G06F13/28

    摘要： An embodiment of a method for terminating direct memory access transfers from system memory to a video device includes completing a current byte transfer from a graphics controller to a video device and then refraining from initiating any further write cycles associated with a DMA transfer to the video device. The graphics controller then allows uninterrupted or atomic read and write cycles to the video device. The graphics controller also completes any current read cycles on a system bus that had previously been initiated. The graphics controller then resets its DMA engine and invalidates all information in a first-in, first-out (FIFO) storage buffer.

    摘要翻译： 用于终止从系统存储器到视频设备的直接存储器访问传输的方法的实施例包括完成从图形控制器到视频设备的当前字节传输，然后避免发起与DMA传输到视频设备相关联的任何进一步的写周期 。 然后，图形控制器允许对视频设备的不间断或原子读取和写入周期。 图形控制器还完成了先前已启动的系统总线上的任何当前读取周期。 图形控制器然后重置其DMA引擎，并使先入先出（FIFO）存储缓冲区中的所有信息无效。

    Method and apparatus for interrupt/SMI# ordering
    5.
    发明授权
    Method and apparatus for interrupt/SMI# ordering 失效
    中断/ SMI＃排序的方法和装置

    公开(公告)号：US5551044A

    公开(公告)日：1996-08-27

    申请号：US349065

    申请日：1994-12-01

    申请人： Nilesh V. Shah ,  Jeffrey L. Rabe ,  Zohar Bogin

    发明人： Nilesh V. Shah ,  Jeffrey L. Rabe ,  Zohar Bogin

    IPC分类号： G06F13/24 ,  G06F13/00

    CPC分类号： G06F13/24

    摘要： A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.

    摘要翻译： 用于控制计算机系统中的中断请求信号传输的电路。 输入接收来自外部组件的中断请求。 耦合到输入的第一电路响应于来自外部组件的中断请求而生成信号。 信号使处理器切换到完全运行模式。 耦合到输入的第二电路响应于来自外部组件的中断请求，向处理器生成中断请求信号。 耦合到第二电路的信号处理电路抑制中断请求信号到处理器的传输，直到信号被发送到处理器。

    Method and apparatus for providing concurrent access by a plurality of agents to a shared memory
    6.
    发明授权
    Method and apparatus for providing concurrent access by a plurality of agents to a shared memory 失效
    用于提供由多个代理程序并发访问共享存储器的方法和装置

    公开(公告)号：US5815167A

    公开(公告)日：1998-09-29

    申请号：US672099

    申请日：1996-06-27

    申请人： Manish Muthal ,  Nilesh V. Shah ,  Kuljit Bains

    发明人： Manish Muthal ,  Nilesh V. Shah ,  Kuljit Bains

    IPC分类号： G06T1/60 ,  G06F12/06 ,  G06F13/16 ,  G06F13/18 ,  G06F15/16 ,  G06F15/167 ,  G06T1/20 ,  G09G5/00

    CPC分类号： G06F15/167 ,  G06F13/1647

    摘要： A computer system, including a graphics controller and a memory controller, employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form a bank of DRAMs. The shared memory is accessible by both the memory and graphics controllers. The memory includes a shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined. An interface selectively provides access to the shared DRAM row by the graphics or memory controller, while providing permanent access to the remaining DRAM rows by the memory controller. This facilitates concurrent access by the graphics controller and the memory controller to the shared DRAM row and to the remaining DRAM rows respectively, in a first memory access scenario. The accessibility of the shared DRAM row by the memory controller, in a second memory access scenario, is also maintained. The interface includes a selector circuit, such as a multiplexor or Q-switch, coupled to receive memory address signals and control signals from the graphics controller and the memory controller via a dedicated bus from each of these controllers. The selector circuit is operable selectively to present either memory address to the shared DRAM row, in which the SFB aperture is defined, and also selectively to provide access to the shared DRAM row by either controller. The selector circuit is operable by a logic circuit, incorporated within the systems controller, which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row, or in the remaining DRAM rows.

    摘要翻译： 包括图形控制器和存储器控制器的计算机系统采用共享帧缓冲器架构，因此具有一组DRAM形式的共享存储器。 共享内存可由内存和图形控制器访问。 存储器包括共享DRAM行，其中定义了共享帧缓冲器（SFB）孔径。 接口选择性地提供对图形或存储器控制器对共享DRAM行的访问，同时由存储器控制器永久地访问剩余的DRAM行。 这有助于在第一存储器访问场景中分别由图形控制器和存储器控制器同时访问共享的DRAM行和剩余的DRAM行。 在第二存储器访问场景中，存储器控制器的共享DRAM行的可访问性也被保持。 该接口包括诸如多路复用器或Q开关的选择器电路，其经由来自这些控制器中的每一个的专用总线耦合以从图形控制器和存储器控制器接收存储器地址信号和控制信号。 选择器电路可选择地可操作地将存储器地址呈现给共享DRAM行，其中定义了SFB孔径，并且还选择性地通过任一控制器提供对共享DRAM行的访问。 选择器电路可由逻辑电路操作，该逻辑电路包括在系统控制器内，该逻辑电路确定从存储器控制器接收到的存储器访问请求是否是共享DRAM行中的地址或剩余的DRAM行中的地址。

    Method and apparatus for control of power consumption in a computer system
    7.
    发明授权
    Method and apparatus for control of power consumption in a computer system 失效
    用于控制计算机系统中功耗的方法和装置

    公开(公告)号：US5655127A

    公开(公告)日：1997-08-05

    申请号：US612673

    申请日：1996-03-08

    申请人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

    发明人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1282 ,  Y02B60/32

    摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.

    摘要翻译： 一种具有响应低功率模式和全功率工作模式的计算机系统。 计算机系统包括功率消耗控制器，处理器和通信设备。 功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。 功耗控制器还产生时钟控制信号。 时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。 响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块 处理器。 通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

    Method and apparatus for power managing display devices
    10.
    发明授权
    Method and apparatus for power managing display devices 失效
    电源管理显示设备的方法和装置

    公开(公告)号：US06603480B1

    公开(公告)日：2003-08-05

    申请号：US09223041

    申请日：1998-12-30

    申请人： Nilesh V. Shah

    发明人： Nilesh V. Shah

    IPC分类号： G06F1500

    CPC分类号： G06F3/14 ,  G09G2330/021 ,  G09G2370/04

    摘要： An embodiment of a graphics controller includes a clock output circuit to output a clock signal and also includes a display device control signal input/output circuit to output a display device control signal. The graphics controller further includes a display device data bus input/output circuit to output an encoded information on a display device data bus when the display device control signal output circuit asserts the display device control signal, the encoded information to represent a power management state.

    摘要翻译： 图形控制器的实施例包括用于输出时钟信号的时钟输出电路，并且还包括用于输出显示装置控制信号的显示装置控制信号输入/输出电路。 图形控制器还包括显示设备数据总线输入/输出电路，用于当显示设备控制信号输出电路断言显示设备控制信号时，将编码信息输出到显示设备数据总线上，该编码信息表示电源管理状态。