公开(公告)号：US5655127A

公开(公告)日：1997-08-05

申请号：US612673

申请日：1996-03-08

申请人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

发明人： Jeffrey L. Rabe ,  Zohar Bogin ,  Ajay V. Bhatt ,  James P. Kardach ,  Nilesh V. Shah

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/3287 ,  Y02B60/1282 ,  Y02B60/32

摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.

摘要翻译： 一种具有响应低功率模式和全功率工作模式的计算机系统。 计算机系统包括功率消耗控制器，处理器和通信设备。 功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。 功耗控制器还产生时钟控制信号。 时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。 响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块 处理器。 通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

公开(公告)号：US09865233B2

公开(公告)日：2018-01-09

申请号：US12346759

申请日：2008-12-30

申请人： Seh W. Kwa ,  James P. Kardach

发明人： Seh W. Kwa ,  James P. Kardach

IPC分类号： G09G5/36 ,  G09G5/00

CPC分类号： G09G5/36 ,  G09G5/003 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2360/06 ,  G09G2360/10 ,  G09G2360/18

摘要： Some embodiments describe techniques that relate to hybrid graphics display power management. In one embodiment, data corresponding to one or more image frames of a video stream are stored in a local frame buffer. A display device (e.g., an LCD) may then be driven based on the stored data in the local frame buffer or a video stream from a graphics controller. Other embodiments are also described.

公开(公告)号：US20140185156A1

公开(公告)日：2014-07-03

申请号：US13729221

申请日：2012-12-28

申请人： James P. Kardach ,  KIRSTY MACDONALD ,  PETER GIBSON

发明人： James P. Kardach ,  KIRSTY MACDONALD ,  PETER GIBSON

IPC分类号： G11B19/28

CPC分类号： G11B19/28

摘要： Various embodiments are generally directed recurringly cycling the driving of a platter media of a hard drive with a motor, allowing rotation of the platter media to slow only to a threshold rotational speed to balance power conservation with delays in accessing data. A method comprises driving platter media of a hard drive to rotate at a selected normal rotational speed, retrieving data stored on the platter media when the platter media rotates at the normal rotational speed, ceasing to drive the platter media to rotate to allow the platter media to rotate under rotational inertia imparted to the platter media, monitoring a current rotational speed of the platter media, and resuming driving the platter media to rotate based on the current rotational speed falling to a lower threshold rotational speed selected to be less than the normal rotational speed. Other embodiments are described and claimed.

摘要翻译： 各种实施例通常定期循环利用电动机驱动硬盘驱动器的盘片介质，允许盘片介质的旋转仅减慢到阈值旋转速度以平衡功率节省与访问数据的延迟。 一种方法包括驱动硬盘驱动器的盘式介质以选定的正常转速旋转，当盘式介质以正常转速旋转时检索存储在盘片介质上的数据，停止驱动盘式介质旋转以允许盘片介质 在旋转惯性下旋转到盘片介质上，监测盘片介质的当前旋转速度，并且基于当前旋转速度下降到低于正常旋转的较低阈值旋转速度，重新开始驱动盘片介质旋转 速度。 描述和要求保护其他实施例。

公开(公告)号：US08484488B2

公开(公告)日：2013-07-09

申请号：US12326775

申请日：2008-12-02

申请人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

发明人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

公开(公告)号：US08156351B2

公开(公告)日：2012-04-10

申请号：US12326775

申请日：2008-12-02

申请人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

发明人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC分类号： G06F1/00 ,  G06F1/32

摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

公开(公告)号：US20100083013A1

公开(公告)日：2010-04-01

申请号：US12632548

申请日：2009-12-07

申请人： James P. Kardach ,  Barnes Cooper ,  Seh Kwa ,  Animesh Mishra ,  Paul Diefenbaugh

发明人： James P. Kardach ,  Barnes Cooper ,  Seh Kwa ,  Animesh Mishra ,  Paul Diefenbaugh

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/325

摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.

摘要翻译： 描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。 芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态 插件事件。

公开(公告)号：US20090083554A1

公开(公告)日：2009-03-26

申请号：US12326775

申请日：2008-12-02

申请人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

发明人： Brian V. Belmont ,  Animesh Mishra ,  James P. Kardach

IPC分类号： G06F1/26 ,  G06F12/08 ,  G06F1/32

CPC分类号： G06F9/4418 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3293 ,  G06F9/3867 ,  G06F9/4401 ,  G06F12/0842 ,  G06F13/4282 ,  G06F15/80 ,  Y02D10/151

摘要： An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

摘要翻译： 本发明的实施例是用于动态地交换处理器核心的技术。 第一个核心有一个第一个指令集。 第一个核心以第一个性能级别执行程序。 当触发事件发生时，第一个内核停止执行程序。 第二核心具有与第一指令集兼容的第二指令集，并且具有与第一性能级别不同的第二性能级别。 当第一个核心执行程序时，第二个内核处于掉电状态。 在第一核心停止执行程序之后，电路对第二核心供电，使得第二核心继续在第二性能级别执行程序。

公开(公告)号：US6018803A

公开(公告)日：2000-01-25

申请号：US768913

申请日：1996-12-17

申请人： James P. Kardach

发明人： James P. Kardach

IPC分类号： G06F1/32 ,  G06F11/34

CPC分类号： G06F1/3228 ,  G06F1/3215 ,  G06F11/349 ,  G06F2201/81

摘要： A bus utilization detection circuit and method. An input is configured to be coupled to a bus to detect bus events. A circuit coupled to the input determines a number of bus events during a first sample period to indicate a percent bus utilization. If the number of bus events during the first sample period meets a first predetermined threshold value, then an activity event is generated. In another embodiment, an activity event is generated only if during a second sample period, the number of first sample periods for which the percent bus utilization meets the first threshold value meets a second threshold value.

摘要翻译： 一种总线利用检测电路及方法。 输入被配置为耦合到总线以检测总线事件。 耦合到输入的电路确定在第一采样周期期间的总线事件数量，以指示百分比总线利用率。 如果在第一采样周期期间总线事件的数量满足第一预定阈值，则生成活动事件。 在另一个实施例中，仅当在第二采样周期期间，百分比总线利用率满足第一阈值的第一采样周期的数量满足第二阈值时才产生活动事件。

公开(公告)号：US6014751A

公开(公告)日：2000-01-11

申请号：US841858

申请日：1997-05-05

申请人： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

发明人： James P. Kardach ,  John Horigan ,  Ravi Eakambaram ,  Tosaku Nakanishi ,  Chih-Hung Chung ,  Borys S. Senyk

IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F12/08 ,  G06F1/10

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0835 ,  Y02B60/1217 ,  Y02B60/1221

摘要： A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

摘要翻译： 描述用于操作集成在降低功耗状态的方法和装置。 该装置包括功率降低逻辑，为了将集成电路置于降低功耗状态，将集成电路中的第一组和第二组功能单元的时钟信号置于门限。 第一组功能单元的特征在于需要在集成电路内执行高速缓存一致性操作。 该装置包括输入，该输入被耦合以通过集成电路外部的另外的设备将指示存储器访问的信号接收到由集成电路可访问的存储器资源。 响应于该信号的断言，功率降低逻辑将时钟信号传播到第一组功能单元，以使得该组功能单元能够执行高速缓存一致性操作，这可能由外部存储器访问所必需 设备。

公开(公告)号：US5918043A

公开(公告)日：1999-06-29

申请号：US874559

申请日：1997-06-13

申请人： James P. Kardach ,  Tosaku Nakanishi ,  Jimmy S. Cheng

发明人： James P. Kardach ,  Tosaku Nakanishi ,  Jimmy S. Cheng

IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F1/26 ,  G06F11/00 ,  G06F11/267

CPC分类号： G06F11/2236 ,  G06F1/04 ,  G06F1/10 ,  G06F1/26 ,  G06F11/004

摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

摘要翻译： 用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。 本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应/断言外部引脚。 然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。 中断机制也用于优先考虑外部信号在其他系统中断中的发生。 中断机制确保处理器在总线周期的中间没有停止其时钟。