公开(公告)号：US07911842B2

公开(公告)日：2011-03-22

申请号：US12081568

申请日：2008-04-17

申请人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

发明人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

IPC分类号： G11C16/04

CPC分类号： H01L29/7883 ,  G11C16/10

摘要： Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

摘要翻译： 提供了一种存储器单元编程方法和半导体器件，其可以能够同时将数据位和数据的另一位写入多个存储块。 其中将M位数据写入多个存储块的存储器编程方法可以包括数据分割操作和数据写入操作，其中M可以是自然数。 在数据划分操作中，多个存储块可以被划分为多个存储块组。 在数据写入操作中，数据的第i位可以从多个存储器块组中同时写入两个或更多个存储块组，然后数据的第i + 1位可以被同时写入两个或更多个 多个存储块组中的存储块组，其中i是小于M的自然数。

公开(公告)号：US20080285343A1

公开(公告)日：2008-11-20

申请号：US12081568

申请日：2008-04-17

申请人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

发明人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

IPC分类号： G11C16/04 ,  G11C8/00

CPC分类号： H01L29/7883 ,  G11C16/10

摘要： Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

摘要翻译： 提供了一种存储器单元编程方法和半导体器件，其可以能够同时将数据位和数据的另一位写入多个存储块。 其中将M位数据写入多个存储块的存储器编程方法可以包括数据分割操作和数据写入操作，其中M可以是自然数。 在数据划分操作中，多个存储块可以被划分为多个存储块组。 在数据写入操作中，数据的第i / O位可以被同时写入到多个存储块组之中的两个或更多个存储块组，然后i + 1＆lt; / SUP>位可以从多个存储块组中的两个或更多个存储块组同时写入，其中i是小于M的自然数。

公开(公告)号：US07729175B2

公开(公告)日：2010-06-01

申请号：US12010481

申请日：2008-01-25

申请人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

发明人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5642

摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

摘要翻译： 提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。 对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。 在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。 在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。 在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

公开(公告)号：US20080285352A1

公开(公告)日：2008-11-20

申请号：US12010481

申请日：2008-01-25

申请人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

发明人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5642

摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

摘要翻译： 提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。 对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。 在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。 在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。 在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

公开(公告)号：US20090091974A1

公开(公告)日：2009-04-09

申请号：US12219663

申请日：2008-07-25

申请人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

发明人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

摘要翻译： 一种编程非易失性存储单元的方法包括通过将非易失性存储单元的阈值电压设置为多个阈值电压分布中的第一个内的第一电压电平来对第一位多位数据进行编程。 通过基于第二位的值将阈值电压设置为第二电压电平来编程多位数据的第二位。 如果第二位是第二值，则第二电压电平与第一电压电平相同，如果第二位是第二值，则第二电压电平在多个阈值电压分布的一秒内。 通过将阈值电压设置为基于第三位的值的第三电压电平来编程多位数据的第三位。

公开(公告)号：US07885107B2

公开(公告)日：2011-02-08

申请号：US12219663

申请日：2008-07-25

申请人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

发明人： Ju-hee Park ,  Young-moon Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5648

摘要： A method of programming a non-volatile memory cell includes programming a first bit of multi-bit data by setting a threshold voltage of the non-volatile memory cell to a first voltage level within a first of a plurality of threshold voltage distributions. A second bit of the multi-bit data is programmed by setting the threshold voltage to a second voltage level based on a value of the second bit. The second voltage level is the same as the first voltage level if the second bit is a first value and the second voltage level is within a second of the plurality of threshold voltage distributions if the second bit is a second value. A third bit of the multi-bit data is programmed by setting the threshold voltage to a third voltage level based on a value of the third bit.

摘要翻译： 一种编程非易失性存储单元的方法包括通过将非易失性存储单元的阈值电压设置为多个阈值电压分布中的第一个内的第一电压电平来对第一位多位数据进行编程。 通过基于第二位的值将阈值电压设置为第二电压电平来编程多位数据的第二位。 如果第二位是第二值，则第二电压电平与第一电压电平相同，如果第二位是第二值，则第二电压电平在多个阈值电压分布的一秒内。 通过将阈值电压设置为基于第三位的值的第三电压电平来编程多位数据的第三位。

公开(公告)号：US20080151631A1

公开(公告)日：2008-06-26

申请号：US11980358

申请日：2007-10-31

申请人： Jae-woong Hyun ,  Kyu-charn Park ,  Yoon-dong Park ,  Won-joo Kim ,  Young-gu Jin ,  Suk-pil Kim ,  Kyoung-lae Cho ,  Jung-hoon Lee ,  Seung-hwan Song

发明人： Jae-woong Hyun ,  Kyu-charn Park ,  Yoon-dong Park ,  Won-joo Kim ,  Young-gu Jin ,  Suk-pil Kim ,  Kyoung-lae Cho ,  Jung-hoon Lee ,  Seung-hwan Song

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L27/1203

摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.

摘要翻译： 提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。 非易失性存储器件包括半导体层。 多个上控制栅电极设置在半导体层的上方。 多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。 多个上电荷存储层插入在半导体层和上控制栅电极之间。 多个下电荷存储层插入在半导体层和下控制栅电极之间。

公开(公告)号：US20080157182A1

公开(公告)日：2008-07-03

申请号：US11980632

申请日：2007-10-31

申请人： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-Woong Hyun ,  Sung-jae Byun

发明人： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-Woong Hyun ,  Sung-jae Byun

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

摘要翻译： 示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。 半导体器件包括半导体衬底，半导体柱和接触插塞。 半导体衬底包括至少一对使用（或功能）作为活性区的翅片。 半导体柱可以插入翅片的部分之间以连接散热片。 接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

公开(公告)号：US07829932B2

公开(公告)日：2010-11-09

申请号：US11980632

申请日：2007-10-31

申请人： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-woong Hyun ,  Sung-jae Byun

发明人： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-woong Hyun ,  Sung-jae Byun

IPC分类号： H01L29/788

CPC分类号： H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

摘要翻译： 示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。 半导体器件包括半导体衬底，半导体柱和接触插塞。 半导体衬底包括至少一对使用（或功能）作为活性区的翅片。 半导体柱可以插入翅片的部分之间以连接散热片。 接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

公开(公告)号：US20110038207A1

公开(公告)日：2011-02-17

申请号：US12856698

申请日：2010-08-16

申请人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

发明人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642

摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

摘要翻译： 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。