公开(公告)号：US09882737B2

公开(公告)日：2018-01-30

申请号：US14003518

申请日：2012-01-19

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

IPC分类号： H04L12/40 ,  H04L12/26 ,  G06F13/38

CPC分类号： H04L12/40 ,  G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L43/0817

摘要： A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby.

公开(公告)号：US20140059250A1

公开(公告)日：2014-02-27

申请号：US14003518

申请日：2012-01-19

申请人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

发明人： Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Takashi Yoshikawa ,  Teruyuki Baba ,  Nobuharu Kami

IPC分类号： H04L12/40

CPC分类号： H04L12/40 ,  G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L43/0817

摘要： A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby.

摘要翻译： 本发明的网络系统包括计算机和通过网络连接的设备和系统管理设备。 计算机和设备分别包括封装彼此发送和接收的发送/接收数据的网桥，并经由网络从彼此发送和接收数据。 每个桥包括控制数据发送装置，用于基于从计算机或设备发出的用于控制系统的状态的控制辅助数据产生用于控制系统的状态的控制数据，并将控制数据发送到 系统管理设备通过网络。 系统管理装置包括系统控制装置，用于根据从其接收的控制数据来控制系统的状态。

公开(公告)号：US08868814B2

公开(公告)日：2014-10-21

申请号：US13382262

申请日：2010-06-11

申请人： Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

发明人： Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

IPC分类号： G06F13/20 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4022 ,  G06F2213/0026

摘要： Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself.

摘要翻译： 提高了容错能力，避免了I / O系统启动时的功能限制，缩短启动时间。 下游PCI Express桥接器设置连接到下游PCI Express桥本身的PCI Express设备，其中多个单根根兼容PCI Express设备由连接到多个上游PCI Express桥的多个根配置共享的多个单根根兼容PCI Express设备中， 下游PC Express桥本身通过网络，控制和监视与连接到下游PCI Express桥本身的PCI Express设备的物理链路的状态，并执行连接到下游的PCI Express设备的错误的监视和通知 PCI Express桥本身。

公开(公告)号：US20140245053A1

公开(公告)日：2014-08-28

申请号：US14347489

申请日：2012-06-13

申请人： Takashi Yoshikawa ,  Youichi Hidaka ,  Jun Suzuki ,  Junichi Higuchi

发明人： Takashi Yoshikawa ,  Youichi Hidaka ,  Jun Suzuki ,  Junichi Higuchi

IPC分类号： G06F1/32

CPC分类号： G06F1/3253 ,  G06F13/385 ,  Y02D10/151

摘要： A local computer (20) and a remote I/O device (30) are interconnected on a network (40) through an upstream side bridge (21) and a downstream side bridge (31). The upstream side bridge (21) and the downstream side bridge (31) each include a register (216, 316) for referring to or writing a signal aside from a primary data stream that runs through the network (40) from both sides, and a mechanism (217, 317) for transmitting and receiving the signal aside from the primary data stream inband when referring to or writing the signal in the register (216, 316).

摘要翻译： 本地计算机（20）和远程I / O设备（30）通过上游侧桥接器（21）和下游侧桥接器（31）在网络（40）上互连。 上游侧桥接器（21）和下游侧桥接器（31）各自包括用于参考或写入从两侧穿过网络（40）的主要数据流之外的信号的寄存器（216,316），以及 用于在参考或写入寄存器（216,316）中的信号时，从主数据流带内发送和接收信号的机构（217,317）。

公开(公告)号：US08625615B2

公开(公告)日：2014-01-07

申请号：US12992164

申请日：2009-05-18

申请人： Youichi Hidaka ,  Takashi Yoshikawa ,  Junichi Higuchi ,  Jun Suzuki

发明人： Youichi Hidaka ,  Takashi Yoshikawa ,  Junichi Higuchi ,  Jun Suzuki

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： G06F13/4022

摘要： Provided are a first PCI-PCI bridge that handles Multi Root to connect to a plurality of root complexes; a second PCI-PCI bridge that connects to an endpoint; a virtual PCI Express switch that performs a switching process between the first and second PCI-PCI bridges; and a network control device that transfers data that is to be processed in the virtual PCI Express switch to an external switch through a network without passing through a PCI-PCI bridge.

摘要翻译： 提供了第一个PCI-PCI桥接器，其处理多根以连接到多个根复合体; 连接到端点的第二个PCI-PCI桥; 一个虚拟PCI Express交换机，执行第一和第二PCI-PCI桥之间的切换过程; 以及网络控制装置，其通过网络将通过网络将要在虚拟PCI Express交换机中处理的数据传送到外部交换机，而不通过PCI-PCI桥接器。

公开(公告)号：US08615623B2

公开(公告)日：2013-12-24

申请号：US12376609

申请日：2007-08-08

申请人： Youichi Hidaka ,  Jun Suzuki ,  Junichi Higuchi ,  Takashi Yoshikawa

发明人： Youichi Hidaka ,  Jun Suzuki ,  Junichi Higuchi ,  Takashi Yoshikawa

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.

摘要翻译： 开关（304）包括多个桥（3041,3042,3043,3044,3045）和开关转发机构（20）。 每个桥接器向连接到每个桥接器的设备发送和接收符合PCI express的TLP帧。 交换机转发机制包括分别连接到所述网桥的多个端口（1,2,3,4,5），根据从其中一个桥接器输入的TLP帧上的目的地信息的组合，选择输出端口 多个端口和输入TLP帧的端口，并从所选择的输出端口输出TLP帧。

公开(公告)号：US20080104328A1

公开(公告)日：2008-05-01

申请号：US11928997

申请日：2007-10-30

申请人： Takashi Yoshikawa ,  Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Atsushi Iwata

发明人： Takashi Yoshikawa ,  Jun Suzuki ,  Youichi Hidaka ,  Junichi Higuchi ,  Atsushi Iwata

IPC分类号： G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/0862 ,  G06F2212/602 ,  Y02D10/13

摘要： A local-memory side data transfer unit increments the number of addresses, reads out data from a local memory, and stores the data into a cache memory of a remote-memory side data transfer unit. For preventing data mismatching with the local memory from being stored into the cache memory, a cache clearing operation is executed in units of an elapse of a round trip time period for data transfer between the local memory and the remote memory. Alternatively, the cache clearing operation is executed upon receipt of a signal notifying data transfer of data stored at a specified address.

摘要翻译： 本地存储器侧数据传送单元增加地址数量，从本地存储器读出数据，并将数据存储到远程存储器侧数据传送单元的高速缓冲存储器中。 为了防止与本地存储器的数据不匹配被存储到高速缓冲存储器中，以本地存储器和远程存储器之间的数据传送的往返时间周期为单位执行高速缓存清除操作。 或者，在接收到通知数据传送存储在指定地址的数据的信号时执行高速缓存清除操作。

公开(公告)号：US20120263182A1

公开(公告)日：2012-10-18

申请号：US13531637

申请日：2012-06-25

申请人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

发明人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

IPC分类号： H04L12/56

CPC分类号： H04L1/1841 ,  H04L1/1874 ,  H04L1/188 ,  H04L45/24 ,  H04L45/28 ,  H04L2001/0096

摘要： Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.

摘要翻译： 在多路径环境中只有一系列的序列号，任何分组丢失被非常快速地检测到，其中发射机和接收机通过多个网络彼此连接，当序列的任何 网络。 通信装置包括布置在每个网络处的多个序列缓冲器，用于累积分组，直到序列确认和不存在检测部分适于在所有序列缓冲器中累积一个或多个分组时确定是否存在分组。 利用这种安排，接收机的缺席检测部分监视保留在每个网络中的序列保证缓冲器中的数据包，注意发生分组丢失时分组存储在所有网络的序列缓冲器中的特性 。

公开(公告)号：US20100180062A1

公开(公告)日：2010-07-15

申请号：US12376609

申请日：2007-08-08

申请人： Youichi Hidaka ,  Jun Suzuki ,  Junichi Higuchi ,  Takashi Yoshikawa

发明人： Youichi Hidaka ,  Jun Suzuki ,  Junichi Higuchi ,  Takashi Yoshikawa

IPC分类号： G06F13/36 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.

摘要翻译： 开关（304）包括多个桥（3041,3042,3043,3044,3045）和开关转发机构（20）。 每个桥接器向连接到每个桥接器的设备发送和接收符合PCI express的TLP帧。 交换机转发机制包括分别连接到所述网桥的多个端口（1,2,3,4,5），根据从其中一个桥接器输入的TLP帧上的目的地信息的组合，选择输出端口 多个端口和输入TLP帧的端口，并从所选择的输出端口输出TLP帧。

公开(公告)号：US20090059928A1

公开(公告)日：2009-03-05

申请号：US12200508

申请日：2008-08-28

申请人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

发明人： Nobuyuki Enomoto ,  Hideyuki Shimonishi ,  Junichi Higuchi ,  Youichi Hidaka ,  Jun Suzuki ,  Takashi Yoshikawa

IPC分类号： H04L12/56

CPC分类号： H04L1/1841 ,  H04L1/1874 ,  H04L1/188 ,  H04L45/24 ,  H04L45/28 ,  H04L2001/0096

摘要： Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.

摘要翻译： 在多路径环境中只有一系列的序列号，任何分组丢失被非常快速地检测到，其中发射机和接收机通过多个网络彼此连接，当序列的任何 网络。 通信装置包括布置在每个网络处的多个序列缓冲器，用于累积分组，直到序列确认和不存在检测部分适于在所有序列缓冲器中累积一个或多个分组时确定是否存在分组。 利用这种安排，接收机的不存在检测部分监视保留在每个网络中的序列保证缓冲器中的数据包，注意发生分组丢失时分组存储在所有网络的序列缓冲器中的特性 。