公开(公告)号：US20050130334A1

公开(公告)日：2005-06-16

申请号：US11046424

申请日：2005-01-27

申请人： Jun-Cheng Ko ,  Young-Tong Tsai

发明人： Jun-Cheng Ko ,  Young-Tong Tsai

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/768 ,  G01R31/26 ,  H01L21/4763 ,  H01L21/66

CPC分类号： H01L21/67253 ,  H01J37/32963 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76897

摘要： A bias compensation self-aligned contact (SAC) etch endpoint detecting system is provided. The system includes an etch reactant chamber, an ESC power supply, and a signal processing computer. The etch reactant chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC supports a substrate having an interlevel dielectric (ILD) layer to be etched. The ESC power supply is coupled to the ESC and is configured to function as a bias compensating power supply. The signal processing computer monitors a bias compensation signal generated by the ESC power supply. The etch process to be carried out in the etch reactant chamber is configured to be discontinued when the bias compensation signal is determined to have a previously ascertained characteristic evidencing an etch endpoint of the ILD layer.

摘要翻译： 提供偏置补偿自对准接触（SAC）蚀刻端点检测系统。 该系统包括蚀刻反应物室，ESC电源和信号处理计算机。 蚀刻反应物室包括静电卡盘（ESC），顶部电极和底部电极。 ESC支持具有待蚀刻的层间电介质（ILD）层的衬底。 ESC电源耦合到ESC，并配置为用作偏置补偿电源。 信号处理计算机监视由ESC电源产生的偏置补偿信号。 在蚀刻反应物室中进行的蚀刻工艺被配置为当偏置补偿信号被确定为具有证明ILD层的蚀刻端点的先前确定的特性时被停止。

公开(公告)号：US06861362B2

公开(公告)日：2005-03-01

申请号：US09895566

申请日：2001-06-29

申请人： Jun-Cheng Ko ,  Young-Tong Tsai

发明人： Jun-Cheng Ko ,  Young-Tong Tsai

IPC分类号： H01L21/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/67253 ,  H01J37/32963 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76897

摘要： A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

摘要翻译： 提供了一种用于增强自对准接触（SAC）结构的制造工艺的方法。 该方法包括在衬底的表面上形成晶体管结构。 该方法还包括在衬底的表面上直接形成电介质层，而不在衬底的表面上形成蚀刻停止层。 还包括在等离子体处理室中的等离子体蚀刻穿过介电层的接触孔。 该方法还包括在等离子体蚀刻过程期间监测等离子体处理室的偏置补偿电压，并且在检测到偏置补偿电压中的端点信号变化时停止等离子体蚀刻工艺。

公开(公告)号：US5915198A

公开(公告)日：1999-06-22

申请号：US845872

申请日：1997-04-28

申请人： Jun-Cheng Ko ,  Erik S. Jeng

发明人： Jun-Cheng Ko ,  Erik S. Jeng

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/311

CPC分类号： H01L21/76804 ,  Y10S257/90

摘要： A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used--without the need for a tightly toleranced mask--to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi.sub.2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi.sub.2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi.sub.2 forms a step over the poly-Si layer. A layer of TEOS oxide is then deposited over the step structure and etched, thus forming oxide spacers surrounding the step structure. A second layer of TEOS is deposited and etched forming contact holes with the desired, gentle slopes yielding at the same time wide contact area at the bottom of the hole with improved reliability.

摘要翻译： 公开了与VLSI和ULSI技术中的锥形接触孔相关的方法和结构。 通过利用由步骤形成的两层多晶硅化合物线形成接触孔。 具有步骤的多余半导体线还用氧化物间隔物形成。 然后将所得结构用于在氧化物间隔物之间​​形成接触孔。 由于使用氧化物间隔物而不需要紧密公差的掩模来限定孔的底部处的接触区域，除了形成的锥形边缘之外，还可获得更大的接触面积。 聚硅氧烷选择为包括硅 - 硅化物（WSi2）在多晶硅（poly-Si）上的多层结构。 接下来，通过蚀刻将多硅化物图案化，其配方比刻蚀WSi2的配方更快地刻蚀下面的多晶硅。 因此，蚀刻导致WSi2在多晶硅层上形成台阶的结构。 然后将TEOS氧化物层沉积在台阶结构上并被蚀刻，从而形成围绕台阶结构的氧化物间隔物。 第二层TEOS被沉积并蚀刻形成具有期望的平缓倾斜的接触孔，同时在孔的底部同时具有较宽的接触面积，并提高了可靠性。

公开(公告)号：US5854135A

公开(公告)日：1998-12-29

申请号：US835579

申请日：1997-04-09

申请人： Jun-Cheng Ko

发明人： Jun-Cheng Ko

IPC分类号： H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31116

摘要： An anisotropic RIE procedure for creating a small diameter SAC opening, in an insulator layer, used in the fabrication sequence of a MOSFET device, and using a large area test site for RIE end point monitoring, has been developed. The RIE procedure features a RIE ambient, including oxygen as part of the RIE ambient, resulting in equal amounts of polymer deposition on the small diameter SAC opening, as well as on the large area test sites, during the reactive ion etching of the small diameter, SAC opening. This allows accurate monitoring of the RIE procedure to be performed on the large area test site, using optical ellipsometry procedures.

摘要翻译： 已经开发了用于在MOSFET器件的制造顺序中使用的用于产生在绝缘体层中的小直径SAC开口以及使用用于RIE端点监测的大面积测试部位的各向异性RIE程序。 RIE程序具有RIE环境，包括作为RIE环境的一部分的氧气，导致在小直径的反应离子蚀刻期间在小直径SAC开口以及大面积测试位置上的等量的聚合物沉积 SAC开幕。 这允许使用光学椭圆测量法在大面积测试场地上精确地监测要执行的RIE程序。

公开(公告)号：US06211557B1

公开(公告)日：2001-04-03

申请号：US09277562

申请日：1999-03-26

申请人： Jun-Cheng Ko ,  Erik S. Jeng

发明人： Jun-Cheng Ko ,  Erik S. Jeng

IPC分类号： H01L2976

CPC分类号： H01L21/76804 ,  Y10S257/90

摘要： A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used—without the need for a tightly toleranced mask—to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi2 forms a step over the poly-Si layer. A layer of TEOS oxide is then deposited over the step structure and etched, thus forming oxide spacers surrounding the step structure. A second layer of TEOS is deposited and etched forming contact holes with the desired, gentle slopes yielding at the same time wide contact area at the bottom of the hole with improved reliability.

摘要翻译： 公开了与VLSI和ULSI技术中的锥形接触孔相关的方法和结构。 通过利用由步骤形成的两层多晶硅化合物线形成接触孔。 具有步骤的多余半导体线还用氧化物间隔物形成。 然后将所得结构用于在氧化物间隔物之间​​形成接触孔。 由于使用氧化物间隔物而不需要紧密公差的掩模来限定孔的底部处的接触区域，除了形成的锥形边缘之外，还可获得更大的接触面积。 聚硅氧烷选择为包括硅 - 硅化物（WSi2）在多晶硅（poly-Si）上的多层结构。 接下来，通过蚀刻将多硅化物图案化，其配方比刻蚀WSi2的配方更快地刻蚀下面的多晶硅。 因此，蚀刻导致WSi2在多晶硅层上形成台阶的结构。 然后将TEOS氧化物层沉积在台阶结构上并被蚀刻，从而形成围绕台阶结构的氧化物间隔物。 第二层TEOS被沉积并蚀刻形成具有期望的平缓倾斜的接触孔，同时在孔的底部同时具有较宽的接触面积，并提高了可靠性。

公开(公告)号：US6069077A

公开(公告)日：2000-05-30

申请号：US888636

申请日：1997-07-07

申请人： Daniel Hao-Tien Lee ,  Jun-Cheng Ko

发明人： Daniel Hao-Tien Lee ,  Jun-Cheng Ko

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/0273 ,  H01L21/31144

摘要： A method of forming a self-aligned contact in the fabrication of an integrated circuit is described. Semiconductor device structures are formed on a semiconductor substrate wherein their top and side surfaces are covered by a silicon nitride layer. A diagonal width of the silicon nitride layer on the side surfaces is a critical dimension. A layer of silicon oxide is deposited over the device structures and contacting the substrate adjacent to at least one of the semiconductor device structures where the self-aligned contact is to be formed. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned contact. Thereafter, the photoresist is exposed to ultraviolet light whereby the photoresist layer is cured. The silicon oxide is etched away at a high temperature to provide an opening to the silicon substrate using the patterned and cured photoresist and the silicon nitride layer on the side surfaces as a mask wherein the high temperature provides high selectivity of the silicon nitride layer to the silicon oxide layer and wherein the critical dimension is maintained at a thickness sufficient to prevent a short between the semiconductor device structure and a conducting layer to be deposited within the opening. A conducting layer is deposited within the opening to complete the formation of the self-aligned contact.

摘要翻译： 描述了在集成电路的制造中形成自对准接触的方法。 半导体器件结构形成在半导体衬底上，其顶表面和侧表面被氮化硅层覆盖。 侧面上的氮化硅层的对角宽度是关键尺寸。 在器件结构上沉积氧化硅层，并且与衬底相邻接近要形成自对准接触的至少一个半导体器件结构。 衬底被一层光致抗蚀剂覆盖，该层被图案化以在计划的自对准接触上提供开口。 此后，将光致抗蚀剂暴露于紫外线，由此使光致抗蚀剂层固化。 氧化硅在高温下被蚀刻掉以提供使用图案化和固化的光致抗蚀剂和侧表面上的氮化硅层作为掩模的硅衬底的开口，其中高温提供氮化硅层的高选择性 氧化硅层，其中临界尺寸保持在足以防止半导体器件结构和导电层之间的短路沉积在开口内的厚度。 导电层沉积在开口内以完成自对准接触的形成。

公开(公告)号：US5817579A

公开(公告)日：1998-10-06

申请号：US835577

申请日：1997-04-09

申请人： Jun-Cheng Ko ,  Erik S. Jeng

发明人： Jun-Cheng Ko ,  Erik S. Jeng

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/302

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76897

摘要： A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer through a first reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer through a second reactive ion etch (RIE) method employing a second etchant gas composition comprising carbon tetrafluoride and oxygen. The method may also be employed in general for etching silicon oxide layers in the presence of silicon nitride layers. Similarly, the method may also in general be employed in removing fluorocarbon polymer residue layers from integrated circuit layers including but not limited to silicon oxide layers and silicon nitride layers.

摘要翻译： 一种通过氧化硅层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的氮化硅层，其限定图案化氮化硅层下面的接触。 然后在图案化的氮化硅层上形成氧化硅层。 然后通过使用包括碳氟化合物蚀刻剂气体的第一蚀刻剂气体组合物的第一反应离子蚀刻（RIE）方法蚀刻氧化硅层，以形成：（1）蚀刻氧化硅层，其暴露接触而基本上不蚀刻图案化硅 氮化物层; 和（2）在蚀刻的氧化硅层和图案化氮化硅层中的至少一个上形成的氟碳聚合物残渣层。 最后，通过使用包含四氟化碳和氧气的第二蚀刻剂气体组合物的第二反应离子蚀刻（RIE）方法从基底上剥离氟碳聚合物残余物层。 该方法通常也可用于在存在氮化硅层的情况下蚀刻氧化硅层。 类似地，该方法通常也可用于从包括但不限于氧化硅层和氮化硅层的集成电路层去除碳氟聚合物残余物层。

公开(公告)号：US5788767A

公开(公告)日：1998-08-04

申请号：US777585

申请日：1996-12-31

申请人： Jun-Cheng Ko ,  Liang-Tung Tony Chang

发明人： Jun-Cheng Ko ,  Liang-Tung Tony Chang

IPC分类号： H01L21/318 ,  H01L23/532 ,  C30B23/08

CPC分类号： H01L23/5329 ,  H01L21/3185 ,  H01L2924/0002 ,  Y10S117/905

摘要： The present invention is a method for using a single SiN layer as a passivation film. The single layer SiN can be strengthened to withstand stress by adjusting the process parameters during formation of the SiN layer. In general, the process can be changed by increasing the low frequency power 5% during the deposition. Alternatively, the pressure of the SiN deposition may be decreased about 20% in pressure.

摘要翻译： 本发明是使用单个SiN层作为钝化膜的方法。 可以通过在SiN层的形成期间调整工艺参数来加强单层SiN以承受应力。 通常，可以通过在沉积期间增加5％的低频功率来改变该过程。 或者，SiN沉积的压力可以降低约20％的压力。