公开(公告)号：US20110187757A1

公开(公告)日：2011-08-04

申请号：US13012810

申请日：2011-01-25

申请人： Jung-Ping Yang ,  Chien-Yu Chen ,  Yu-Kuang Chang ,  Hsi-Ming Chen

发明人： Jung-Ping Yang ,  Chien-Yu Chen ,  Yu-Kuang Chang ,  Hsi-Ming Chen

IPC分类号： G09G5/10

CPC分类号： G09G5/10

摘要： A source driving apparatus of a display is disclosed. The source driving apparatus includes a digital-to-analog converter, a selecting signal generator and a voltage selector. The digital-to-analog converter receives a first part display signal of a display signal and a plurality of gamma voltages and selects a first selecting gamma voltage and a second selecting gamma voltage within the gamma voltages according to the first part display signal. The selecting signal generator receives a second part display signal of the display signal expect the first part display signal and a plurality of pulse-width-modulation (PWM) signals. The selecting signal generator selects one of the PWM signals to generate a selecting signal according to the second part display signal. The voltage selector outputs the first selecting gamma voltage or the second selecting gamma voltage according to a pulse width of the selecting signal.

摘要翻译： 公开了一种显示器的源驱动装置。 源极驱动装置包括数模转换器，选择信号发生器和电压选择器。 数模转换器接收显示信号和多个伽马电压的第一部分显示信号，并根据第一部分显示信号选择伽马电压内的第一选择伽玛电压和第二选择伽玛电压。 选择信号发生器接收期望第一部分显示信号和多个脉冲宽度调制（PWM）信号的显示信号的第二部分显示信号。 选择信号发生器根据第二部分显示信号选择一个PWM信号以产生选择信号。 电压选择器根据选择信号的脉冲宽度输出第一选择伽马电压或第二选择伽玛电压。

公开(公告)号：US08976611B2

公开(公告)日：2015-03-10

申请号：US13837614

申请日：2013-03-15

申请人： Jung-Ping Yang ,  Chia-En Huang ,  Fu-An Wu ,  Chih-Chieh Chiu ,  Cheng Hung Lee

发明人： Jung-Ping Yang ,  Chia-En Huang ,  Fu-An Wu ,  Chih-Chieh Chiu ,  Cheng Hung Lee

IPC分类号： G11C7/00 ,  G11C7/06 ,  G06F17/50 ,  G11C7/10 ,  G11C7/12 ,  G11C11/419

CPC分类号： G11C7/065 ,  G06F17/5063 ,  G06F17/5081 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/419

摘要： A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.

摘要翻译： 用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。 存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。 第一和第二节点分别耦合到第一和第二位线。 输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流 响应于从存储器单元读出的第二数据的电压。 输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。 第一个电流大于第二个电流。

公开(公告)号：US09058858B2

公开(公告)日：2015-06-16

申请号：US13303231

申请日：2011-11-23

申请人： Hong-Chen Cheng ,  Chia-En Huang ,  Chih-Chieh Chiu ,  Jung-Ping Yang

发明人： Hong-Chen Cheng ,  Chia-En Huang ,  Chih-Chieh Chiu ,  Jung-Ping Yang

IPC分类号： G11C11/418 ,  G11C8/10 ,  G11C11/413

CPC分类号： G11C8/10 ,  G11C11/413 ,  G11C11/418

摘要： An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.

摘要翻译： 一种装置包括电平移位器和开关电路。 电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。 切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。 开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。

公开(公告)号：US08982609B2

公开(公告)日：2015-03-17

申请号：US13372099

申请日：2012-02-13

申请人： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

发明人： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

IPC分类号： G11C11/00

CPC分类号： G11C11/4094 ,  G11C11/419

摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

摘要翻译： 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

公开(公告)号：US08675439B2

公开(公告)日：2014-03-18

申请号：US13271353

申请日：2011-10-12

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC分类号： G11C5/14

CPC分类号： G11C7/12 ,  G11C11/419

摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

摘要翻译： 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

公开(公告)号：US08385136B2

公开(公告)日：2013-02-26

申请号：US12913087

申请日：2010-10-27

申请人： Cheng Hung Lee ,  Jung-Ping Yang

发明人： Cheng Hung Lee ,  Jung-Ping Yang

IPC分类号： G11C5/14

CPC分类号： G11C7/12 ,  G11C7/067

摘要： The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.

摘要翻译： 本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。 此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。 类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。 存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。

公开(公告)号：US20080316199A1

公开(公告)日：2008-12-25

申请号：US11963855

申请日：2007-12-24

申请人： Jung-Ping Yang

发明人： Jung-Ping Yang

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G5/395 ,  G09G2330/021

摘要： To reduce power consumption and enhance memory-data transmission efficiency, the present invention provides a circuit system for reading memory data for a display device includes a memory, a data bus and a latch circuit. The memory is used for storing pixel data corresponding to a plurality of pixels and outputting the pixel data according to an output control signal. The data bus is used for transferring the pixel data outputted by the memory. The latch circuit is coupled to the data bus and used for receiving the pixel data from the data bus. The latch circuit includes a plurality of latchers and a plurality of logic circuits. The plurality of latchers is used for storing the pixel data. The plurality of logic circuits is used for performing logic operations on the pixel data stored in the plurality of latchers according to a reading control signal.

摘要翻译： 为了降低功耗并提高存储器数据传输效率，本发明提供了一种用于读取用于显示设备的存储器数据的电路系统，包括存储器，数据总线和锁存电路。 存储器用于存储与多个像素相对应的像素数据，并根据输出控制信号输出像素数据。 数据总线用于传送由存储器输出的像素数据。 锁存电路耦合到数据总线，用于从数据总线接收像素数据。 锁存电路包括多个锁存器和多个逻辑电路。 多个拉闸器用于存储像素数据。 多个逻辑电路用于根据读取控制信号对存储在多个锁存器中的像素数据执行逻辑运算。

公开(公告)号：US08792292B2

公开(公告)日：2014-07-29

申请号：US13046625

申请日：2011-03-11

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C29/00

CPC分类号： G11C29/846

摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

摘要翻译： 电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行 地址。 第一比较器被配置为接收和比较第一行地址和第三行地址。 第二比较器被配置为接收和比较第二行地址和第三行地址。 第一行地址和第二行地址是存储器中的失败行地址。

公开(公告)号：US20130094307A1

公开(公告)日：2013-04-18

申请号：US13271353

申请日：2011-10-12

申请人： Hong-Chen CHENG ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

发明人： Hong-Chen CHENG ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/419

摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

摘要翻译： 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

公开(公告)号：US20120230127A1

公开(公告)日：2012-09-13

申请号：US13046625

申请日：2011-03-11

申请人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chung-Ji Lu ,  Derek C. Tao ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C29/04

CPC分类号： G11C29/846

摘要： A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

摘要翻译： 电路包括被配置为存储第一行地址的故障地址寄存器，耦合到故障地址寄存器的行地址修改器，其中行地址修改器被配置为修改从故障地址寄存器接收的第一行地址以生成第二行 地址。 第一比较器被配置为接收和比较第一行地址和第三行地址。 第二比较器被配置为接收和比较第二行地址和第三行地址。 第一行地址和第二行地址是存储器中的失败行地址。