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18 条记录 (耗时 0.022 秒)

    Method for forming tungsten contact plug
    4.
    发明授权
    Method for forming tungsten contact plug 有权
    形成钨接触塞的方法

    公开(公告)号：US07199019B2

    公开(公告)日：2007-04-03

    申请号：US11002682

    申请日：2004-12-03

    申请人： Ji-Soon Park ,  Hyun-Seok Lim ,  Eung-Joon Lee ,  Jung-Wook Kim

    发明人： Ji-Soon Park ,  Hyun-Seok Lim ,  Eung-Joon Lee ,  Jung-Wook Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/28562 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76876 ,  H01L21/76879 ,  H01L2221/1089

    摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.

    摘要翻译： 一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层 改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨 在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

    Method for forming tungsten contact plug
    5.
    发明申请
    Method for forming tungsten contact plug 有权
    形成钨接触塞的方法

    公开(公告)号：US20050146045A1

    公开(公告)日：2005-07-07

    申请号：US11002682

    申请日：2004-12-03

    申请人： Ji-Soon Park ,  Hyun-Seok Lim ,  Eung-Joon Lee ,  Jung-Wook Kim

    发明人： Ji-Soon Park ,  Hyun-Seok Lim ,  Eung-Joon Lee ,  Jung-Wook Kim

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/28562 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76876 ,  H01L21/76879 ,  H01L2221/1089

    摘要： A method for forming a tungsten contact plug of a semiconductor device including depositing an insulating layer on a semiconductor substrate, etching the insulating layer to form a contact hole, which exposes a conductive region, forming a barrier layer on the semiconductor substrate having the contact hole, changing characteristics of a portion of the barrier layer on the insulating layer and the portion of the barrier layer in the contact hold such that the characteristics between the barrier layer on the insulating layer and the barrier layer in the contact hole differ, depositing a tungsten layer for forming the tungsten contact plug, on the barrier layer, and removing the tungsten layer from the upper portion of the insulating layer to planarize the semiconductor device.

    摘要翻译： 一种用于形成半导体器件的钨接触插塞的方法，包括在半导体衬底上沉积绝缘层，蚀刻绝缘层以形成接触孔，其暴露导电区域，在具有接触孔的半导体衬底上形成阻挡层 改变绝缘层上的阻挡层的一部分和接触保持部中阻挡层的部分的特性，使得绝缘层上的阻挡层与接触孔中的阻挡层之间的特性不同，沉积钨 在阻挡层上形成钨接触塞的层，以及从绝缘层的上部去除钨层以使半导体器件平坦化。

    Stacked semiconductor device and method of manufacturing the same
    6.
    发明申请
    Stacked semiconductor device and method of manufacturing the same 审中-公开
    叠层半导体器件及其制造方法

    公开(公告)号：US20060264025A1

    公开(公告)日：2006-11-23

    申请号：US11434146

    申请日：2006-05-16

    申请人： Jung-Wook Kim

    发明人： Jung-Wook Kim

    IPC分类号： H01L21/4763 ,  H01L23/48

    CPC分类号： H01L23/485 ,  H01L21/76846 ,  H01L21/76898 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a stacked semiconductor device and method of manufacturing the same, an insulation multilayer pattern is formed on a substrate. The insulation multilayer pattern includes a first insulating interlayer pattern, a second insulating interlayer pattern and an opening exposing a surface of the substrate. A first channel pattern may be interposed between the first insulating interlayer pattern and the second insulating interlayer pattern, with a sidewall of the channel pattern being exposed through the opening. A barrier metal layer including a first continuous sub-layer is provided along a sidewall and bottom surface of the opening. The first sub-layer may have a substantially uniform thickness around the first channel pattern.

    摘要翻译： 在层叠半导体器件及其制造方法中，在基板上形成绝缘多层图案。 绝缘多层图案包括第一绝缘层间图案，第二绝缘层间图案和暴露基板表面的开口。 可以在第一绝缘层间图案和第二绝缘层间图案之间插入第一沟槽图案，通道图案的侧壁通过开口露出。 沿着开口的侧壁和底表面设置包括第一连续子层的阻挡金属层。 第一子层可以围绕第一通道图案具有基本均匀的厚度。

    Capacitor for a semiconductor device and method of forming the same
    7.
    发明授权
    Capacitor for a semiconductor device and method of forming the same 有权
    用于半导体器件的电容器及其形成方法

    公开(公告)号：US07719045B2

    公开(公告)日：2010-05-18

    申请号：US12251352

    申请日：2008-10-14

    申请人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

    发明人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

    IPC分类号： H01L27/108

    CPC分类号： H01L28/90 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/75

    摘要： In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.

    摘要翻译： 在具有高介电常数的电容器中，电容器包括圆柱形下电极，电介质层和上电极。 在作为电介质层的下电极的内表面，顶面和外表面上形成金属氧化物层。 第一子电极沿着下电极的轮廓在电介质层的表面上形成，并且第二子电极连续形成在与下电极的顶表面对应的第一子电极上，因此开口部分 的下部电极被第二子电极覆盖。 第一和第二子电极分别包括施加第一和第二应力的第一和第二金属氮化物层。 第一和第二个应力的方向彼此相反。 因此，在具有高介电常数的上电极中破裂最小化，从而减少电流泄漏。

    Method of forming a lower electrode of a capacitor
    8.
    发明授权
    Method of forming a lower electrode of a capacitor 有权
    形成电容器的下电极的方法

    公开(公告)号：US07629262B2

    公开(公告)日：2009-12-08

    申请号：US11282193

    申请日：2005-11-18

    申请人： Jung-Wook Kim ,  Young-Joo Cho

    发明人： Jung-Wook Kim ,  Young-Joo Cho

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L28/91 ,  H01L27/10852

    摘要： In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

    摘要翻译： 在一个实施例中，在半导体存储器件中形成电容器的下电极的方法包括将模具氧化物层蚀刻成具有圆柱形结构，导致具有增加的表面积的电极。 圆柱形结构可以具有多于一个的半径。 这种增加的表面积导致增加的电容。 避免了由于牺牲氧化物层以比模具氧化物层更高的速率蚀刻而发生的过度蚀刻现象。

    Capacitor for a semiconductor device and method of forming the same
    9.
    发明申请
    Capacitor for a semiconductor device and method of forming the same 失效
    用于半导体器件的电容器及其形成方法

    公开(公告)号：US20060113580A1

    公开(公告)日：2006-06-01

    申请号：US11286316

    申请日：2005-11-23

    申请人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

    发明人： Young-Joo Cho ,  Hyun-Seok Lim ,  Rak-Hwan Kim ,  Jung-Wook Kim ,  Hyun-Suk Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L28/90 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/75

    摘要： In a capacitor having a high dielectric constant, the capacitor includes a cylindrical lower electrode, a dielectric layer and an upper electrode. A metal oxide layer is formed on inner, top and outer surfaces of the lower electrode as the dielectric layer. A first sub-electrode is formed on a surface of the dielectric layer along the profile of the lower electrode and a second sub-electrode is continuously formed on the first sub-electrode corresponding to the top surface of the lower electrode, so an opening portion of the lower electrode is covered with the second sub-electrode. The first and second sub-electrodes include first and second metal nitride layers in which first and second stresses are applied, respectively. Directions of the first and second stresses are opposite to each other. Accordingly, cracking is minimized in the upper electrode with the high dielectric constant, thereby reducing current leakage.

    摘要翻译： 在具有高介电常数的电容器中，电容器包括圆柱形下电极，电介质层和上电极。 在作为电介质层的下电极的内表面，顶面和外表面上形成金属氧化物层。 第一子电极沿着下电极的轮廓在电介质层的表面上形成，并且第二子电极连续形成在与下电极的顶表面对应的第一子电极上，因此开口部分 的下部电极被第二子电极覆盖。 第一和第二子电极分别包括施加第一和第二应力的第一和第二金属氮化物层。 第一和第二个应力的方向彼此相反。 因此，在具有高介电常数的上电极中破裂最小化，从而减少电流泄漏。

    Method of forming a lower electrode of a capacitor
    10.
    发明申请
    Method of forming a lower electrode of a capacitor 有权

    公开(公告)号：US20060115946A1

    公开(公告)日：2006-06-01

    申请号：US11282193

    申请日：2005-11-18

    申请人： Jung-Wook Kim ,  Young-Joo Cho

    发明人： Jung-Wook Kim ,  Young-Joo Cho

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/10852

    摘要： In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.