公开(公告)号：US20100308761A1

公开(公告)日：2010-12-09

申请号：US12796094

申请日：2010-06-08

申请人： Junko WAKABAYASHI ,  Masashi Tokuda

发明人： Junko WAKABAYASHI ,  Masashi Tokuda

IPC分类号： H02P6/08

CPC分类号： H02P27/08 ,  H02P6/085

摘要： A disclosed motor driver control device is configured to control a plurality of switching devices that drive a motor. The motor driver control device includes a duty control unit configured to restrict a duty of a first pulse width modulation signal generated by comparing an oscillator signal generated at a predetermined cycle and a pulse generator signal so as to generate a second pulse width modulation signal, and a switching device control signal generator unit configured to include a logic circuit that operates the second pulse width modulation signal as a clock and configured to generate a switching device control signal controlling the plurality of switching devices based on the clock of the logic circuit of the switching device control signal generator unit.

摘要翻译： 所公开的电动机驱动器控制装置被配置为控制驱动电动机的多个开关装置。 电动机驱动器控制装置包括占空比控制单元，其被配置为通过比较以预定周期生成的振荡器信号和脉冲发生器信号而产生的第一脉冲宽度调制信号的占空比，以产生第二脉冲宽度调制信号， 开关装置控制信号发生器单元，被配置为包括将第二脉冲宽度调制信号作为时钟进行操作的逻辑电路，并且被配置为基于切换逻辑电路的时钟产生控制多个开关装置的开关装置控制信号 设备控制信号发生器单元。

公开(公告)号：US08912741B2

公开(公告)日：2014-12-16

申请号：US12796094

申请日：2010-06-08

申请人： Junko Wakabayashi ,  Masashi Tokuda

发明人： Junko Wakabayashi ,  Masashi Tokuda

IPC分类号： H02P1/04 ,  H02P27/08 ,  H02P6/08

CPC分类号： H02P27/08 ,  H02P6/085

摘要： A disclosed motor driver control device is configured to control a plurality of switching devices that drive a motor. The motor driver control device includes a duty control unit configured to restrict a duty of a first pulse width modulation signal generated by comparing an oscillator signal generated at a predetermined cycle and a pulse generator signal so as to generate a second pulse width modulation signal, and a switching device control signal generator unit configured to include a logic circuit that operates the second pulse width modulation signal as a clock and configured to generate a switching device control signal controlling the plurality of switching devices based on the clock of the logic circuit of the switching device control signal generator unit.

摘要翻译： 所公开的电动机驱动器控制装置被配置为控制驱动电动机的多个开关装置。 电动机驱动器控制装置包括占空比控制单元，其被配置为通过比较以预定周期产生的振荡器信号和脉冲发生器信号而产生的第一脉冲宽度调制信号的占空比，以产生第二脉冲宽度调制信号， 开关装置控制信号发生器单元，被配置为包括将第二脉冲宽度调制信号作为时钟进行操作的逻辑电路，并且被配置为基于切换逻辑电路的时钟产生控制多个开关装置的开关装置控制信号 设备控制信号发生器单元。

公开(公告)号：US20120126735A1

公开(公告)日：2012-05-24

申请号：US13384706

申请日：2010-09-03

申请人： Yasuo Ueda ,  Masashi Tokuda ,  Toshihiro Tsukagoshi

发明人： Yasuo Ueda ,  Masashi Tokuda ,  Toshihiro Tsukagoshi

IPC分类号： H02P6/08 ,  H03L7/00

CPC分类号： H02M1/38 ,  H03K5/1515 ,  H03K17/16

摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

摘要翻译： 死时间发生电路包括恒流电路; 产生电容器充电电流的电流产生电路; 以及接收死区时间控制信号和比较器信号的控制电路。 控制电路基于死区时间控制信号和比较器信号产生死区时间产生信号，并且基于死区时间产生信号产生充电/放电信号。 电容器的充电或放电根据充电/放电信号由电容器充电电流控制。 将电容器的电压与阈值电压进行比较，以便当电容器的电压超过阈值电压时产生比较器信号。 控制电路在从死区时间控制信号的上升或下降定时经过延迟时间直到控制电路接收到比较器信号为止的时间开始产生充电/放电信号。

公开(公告)号：US20180241903A1

公开(公告)日：2018-08-23

申请号：US15834665

申请日：2017-12-07

申请人： Masashi Tokuda

发明人： Masashi Tokuda

IPC分类号： H04N1/21 ,  B41J2/47 ,  G02B26/12 ,  B41J2/44 ,  G06K15/12 ,  H04N1/053 ,  G03G15/30 ,  H04N1/00

摘要： A pixel clock generating device includes a high-frequency clock generator, a comparer, a pixel clock generator, and a value switcher. The high-frequency clock generator is configured to generate a high-frequency clock. The comparer is configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value. The pixel clock generator is configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error. The value switcher, including a plurality of groups of values with which the pixel clock is generated, is configured to switch between the plurality of groups of values according to a switching signal after the trailing-end synchronizing signal is inputted, the comparer calculates the error, and the pixel clock generator corrects the pixel clock.

公开(公告)号：US5861824A

公开(公告)日：1999-01-19

申请号：US776994

申请日：1997-02-06

申请人： Tadanori Ryu ,  Masashi Tokuda

发明人： Tadanori Ryu ,  Masashi Tokuda

IPC分类号： H04N1/411 ,  G06T9/00 ,  H03M7/30 ,  H03M7/48 ,  H04N1/41 ,  H03M7/00

CPC分类号： H03M7/48 ,  G06T9/005 ,  H04N1/41

摘要： In S2, to-be-compressed image data is encoded and thus compressed each time when using a respective one of a plurality of templates. In S4, compression rates of encoded data are compared with each other which encoded data was encoded each time when a respective one of the plurality of templates was used in S2. In S6, encoded data having the highest compression rate and template identification information of a template used when the encoded data having the highest compression rate was obtained in S2 are output. The encoding comprises entropy encoding. The to-be-compressed data comprises video game software programs.

摘要翻译： PCT No.PCT / JP96 / 01661 Sec。 371日期1997年2月6日 102（e）1997年2月6日PCT PCT 1996年6月17日PCT公布。 公开号WO97 / 01237 日期1997年1月9日在S2中，每当使用多个模板中的相应一个模板时，被压缩的图像数据被编码并因此被压缩。 在S4中，每当在S2中使用多个模板中的相应一个模板时，编码数据的压缩率彼此进行比较，编码数据被编码。 在S6中，输出在S2中获得具有最高压缩率的编码数据时使用的具有最高压缩率的编码数据和模板识别信息。 编码包括熵编码。 要压缩的数据包括视频游戏软件程序。

公开(公告)号：US09996021B2

公开(公告)日：2018-06-12

申请号：US15427122

申请日：2017-02-08

申请人： Masashi Tokuda

发明人： Masashi Tokuda

IPC分类号： G03G15/04 ,  H04N1/06 ,  H04N1/29 ,  H04N1/047 ,  H04N1/053

CPC分类号： G03G15/04036 ,  H04N1/047 ,  H04N1/053 ,  H04N1/06 ,  H04N1/295 ,  H04N2201/0091 ,  H04N2201/047 ,  H04N2201/0471

摘要： An optical writing device and an image forming apparatus incorporating the optical writing device. The optical writing device includes two or more light sources, a pixel clock generator to measure a scanning speed of one of the two or more light sources and generate a pixel clock of a cycle corrected according to the measured scanning speed, a pulse data generation and output unit to generate pulse width data and shift data for the pixel clock generated by the pixel clock generator to output the generated pulse width data and the generated shift data for each one of the two or more light sources, and a plurality of image pulse generation and output units to generate an image pulse. In the optical writing device, the plurality of image pulse generation and output units are supplied with the pixel clock in common.

公开(公告)号：US07580160B2

公开(公告)日：2009-08-25

申请号：US10763707

申请日：2004-01-22

申请人： Masashi Tokuda

发明人： Masashi Tokuda

IPC分类号： H04N1/32 ,  H04M11/00

CPC分类号： H04N1/32704

摘要： A facsimile use modem apparatus includes an analog interface formed from a silicon data access arrangement interfacing with an analog telephone line. A digital interface is provided to interface with an ISDN line. A signal converting device is provided to convert a modem signal used in facsimile communications via the analog telephone line into a signal used in the ISDN line, vice a versa. A data transmitting device is provided to transmit linear data to a monitor via the silicon data access arrangement when G3 facsimile communications are performed via the ISDN line so as to monitor a progress of the G3 facsimile communications.

摘要翻译： 传真使用调制解调器装置包括由与模拟电话线接口的硅数据访问装置形成的模拟接口。 提供数字接口以与ISDN线路接口。 提供信号转换装置，用于将通过模拟电话线的传真通信中使用的调制解调器信号转换为在ISDN线路中使用的信号，反之亦然。 提供数据发送装置，用于经由ISDN线路进行G3传真通信时经由硅数据存取装置将线性数据发送到监视器，以监视G3传真通信的进度。

公开(公告)号：US20070036206A1

公开(公告)日：2007-02-15

申请号：US11501633

申请日：2006-08-09

申请人： Masashi Tokuda ,  Hirofumi Nishi

发明人： Masashi Tokuda ,  Hirofumi Nishi

IPC分类号： H04B1/38

CPC分类号： H04M11/066 ,  H04N1/32765 ,  H04N1/32789

摘要： This patent specification describes a MODEM device which includes a detector configured to detect a synchronization signal transmitted from a source MODEM in a resynchronization process of a primary channel and a timer configured to count up starting from a beginning of a detection of the synchronization signal, and send information to forcibly move into a receiving mode for receiving image data when a time period from the beginning to a completion of the detection of the synchronization signal exceeds a predetermined time period.

摘要翻译： 该专利说明书描述了一种MODEM装置，其包括：检测器，被配置为检测在主信道的再同步处理中从源MODEM发送的同步信号;以及定时器，被配置为从同步信号的检测开始开始计数;以及 当从同步信号的开始到完成的时间段超过预定时间段时，发送信息被强制地进入用于接收图像数据的接收模式。

公开(公告)号：US10698198B2

公开(公告)日：2020-06-30

申请号：US15834665

申请日：2017-12-07

申请人： Masashi Tokuda

发明人： Masashi Tokuda

IPC分类号： B41J2/44 ,  B41J2/47 ,  G02B26/12 ,  G03G15/043 ,  G06K15/12 ,  H04N1/21 ,  H04N1/00 ,  H04N1/053 ,  G03G15/30

摘要： A pixel clock generating device includes a high-frequency clock generator, a comparer, a pixel clock generator, and a value switcher. The high-frequency clock generator is configured to generate a high-frequency clock. The comparer is configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value. The pixel clock generator is configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error. The value switcher, including a plurality of groups of values with which the pixel clock is generated, is configured to switch between the plurality of groups of values according to a switching signal after the trailing-end synchronizing signal is inputted, the comparer calculates the error, and the pixel clock generator corrects the pixel clock.

公开(公告)号：US08719476B2

公开(公告)日：2014-05-06

申请号：US13231128

申请日：2011-09-13

申请人： Masashi Tokuda

发明人： Masashi Tokuda

IPC分类号： G06F13/00

CPC分类号： G06F13/364

摘要： A communication system includes a master device and slave devices. Each slave device includes a request signal generation part configured to, when data to transmit is generated, generate a request signal indicating a transmission request to a master device; and a transmission part configured to transmit the request signal to the master device. The master device includes a request signal reception part configured to receive the request signals from the slave devices; a selection part acting configured to select one of the slave devices according to the request signals received by the reception part; a transmission part configured to transmit a signal indicating to allow data transmission to the slave device selected by the selection part; and a data reception part configured to receive data from the selected slave device.

摘要翻译： 通信系统包括主设备和从设备。 每个从设备包括一个请求信号产生部分，被配置为当产生要发送的数据时，向主设备生成指示发送请求的请求信号; 以及发送部，被配置为将所述请求信号发送到所述主设备。 主设备包括被配置为从从设备接收请求信号的请求信号接收部分; 选择部件，被配置为根据由所述接收部件接收到的所述请求信号来选择所述从设备中的一个; 发送部，被配置为发送指示允许数据发送到由所述选择部选择的所述从属设备的信号; 以及数据接收部，被配置为从所选择的从属设备接收数据。