公开(公告)号：US07352057B2

公开(公告)日：2008-04-01

申请号：US11245920

申请日：2005-10-07

申请人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

发明人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L24/48 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

摘要翻译： 公开了一种在布线基板上具有内部半导体芯片堆叠的半导体模块。 在一个实施例中，半导体芯片堆叠具有被布置成偏移的半导体芯片，半导体芯片具有在其有源顶侧的至少一个边缘区域中的接合连接焊盘。 这些接合连接焊盘通过接合连接电连接到布线基板。 在这种情况下，半导体芯片以偏移的方式堆叠在彼此的顶部，使得接合连接焊盘保持没有层叠在其上的半导体芯片。 在这种情况下，半导体芯片可以是与在不同边缘区域中的中心布置的接触区域的布线结构方面可能不同的例如成对的硅芯片。

公开(公告)号：US20060091518A1

公开(公告)日：2006-05-04

申请号：US11245920

申请日：2005-10-07

申请人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

发明人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

IPC分类号： H01L23/02

CPC分类号： H01L24/48 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

摘要翻译： 公开了一种在布线基板上具有内部半导体芯片堆叠的半导体模块。 在一个实施例中，半导体芯片堆叠具有被布置成偏移的半导体芯片，半导体芯片具有在其有源顶侧的至少一个边缘区域中的接合连接焊盘。 这些接合连接焊盘通过接合连接电连接到布线基板。 在这种情况下，半导体芯片以偏移的方式堆叠在彼此的顶部，使得接合连接焊盘保持没有层叠在其上的半导体芯片。 在这种情况下，半导体芯片可以是与在不同边缘区域中的中心布置的接触区域的布线结构方面可能不同的例如成对的硅芯片。

公开(公告)号：US20060138632A1

公开(公告)日：2006-06-29

申请号：US10518141

申请日：2003-06-10

申请人： Juergen Zacherl ,  Stephan Blaszczak ,  Martin Reiss ,  Sylke Ludewig

发明人： Juergen Zacherl ,  Stephan Blaszczak ,  Martin Reiss ,  Sylke Ludewig

IPC分类号： H01L21/50 ,  H01L23/24

CPC分类号： H01L21/565 ,  H01L23/3142 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral edges of a chip (2) mounted on a substrate are enclosed by a mold coating (6), the casting compound used for the mold coating (6) being linked with the substrate and forming an integrated whole therewith. The invention further relates to a method for producing such a packaging for semiconductor components. The aim of the invention is to provide a packaging for semiconductor components which is characterized by reduced thermomechanical stress and at the same time a substantially improved adhesion of the mold coating to the substrate, thereby allowing for a higher package load. According to the invention, this aim is achieved in that the substrate (1), at least in some areas, has a spongy structure (7) that is provided with pore-type openings and that extends from the surface to the depths of the structure so that the molding material penetrates the substrate (1) by capillary attraction.

摘要翻译： 本发明涉及用于诸如BOC技术等中的FBGA封装的半导体部件的封装，其中至少安装在基板上的芯片（2）的背面和侧边缘被模具涂层（6）包围， 用于模具涂层（6）的铸造复合材料与基材连接并与其形成整体。 本发明还涉及一种用于制造半导体元件用封装的方法。 本发明的目的是提供一种用于半导体部件的封装，其特征在于减少了热机械应力，同时显着改善了模具涂层对基板的粘附性，从而允许更高的封装负载。 根据本发明，该目的的实现是，至少在一些区域中，衬底（1）具有海绵状结构（7），其具有孔型开口并且从表面延伸到结构的深度 使得成型材料通过毛细吸引而穿透基板（1）。

公开(公告)号：US07384822B2

公开(公告)日：2008-06-10

申请号：US10518141

申请日：2003-06-10

申请人： Juergen Zacherl ,  Stephan Blaszczak ,  Martin Reiss ,  Sylke Ludewig

发明人： Juergen Zacherl ,  Stephan Blaszczak ,  Martin Reiss ,  Sylke Ludewig

IPC分类号： H01L21/48

CPC分类号： H01L21/565 ,  H01L23/3142 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a packaging for semiconductor components such as FBGA packages in BOC technology or the like, wherein at least the back and the lateral edges of a chip (2) mounted on a substrate are enclosed by a mold coating (6), the casting compound used for the mold coating (6) being linked with the substrate and forming an integrated whole therewith. The invention further relates to a method for producing such a packaging for semiconductor components. The aim of the invention is to provide a packaging for semiconductor components which is characterized by reduced thermomechanical stress and at the same time a substantially improved adhesion of the mold coating to the substrate, thereby allowing for a higher package load. According to the invention, this aim is achieved in that the substrate (1), at least in some areas, has a spongy structure (7) that is provided with pore-type openings and that extends from the surface to the depths of the structure so that the molding material penetrates the substrate (1) by capillary attraction.

摘要翻译： 本发明涉及用于诸如BOC技术等中的FBGA封装的半导体部件的封装，其中至少安装在基板上的芯片（2）的背面和侧边缘被模具涂层（6）包围， 用于模具涂层（6）的铸造复合材料与基材连接并与其形成整体。 本发明还涉及一种用于制造半导体元件用封装的方法。 本发明的目的是提供一种用于半导体部件的封装，其特征在于减少了热机械应力，同时显着改善了模具涂层对基板的粘附性，从而允许更高的封装负载。 根据本发明，该目的的实现是，至少在一些区域中，衬底（1）具有海绵状结构（7），其具有孔型开口并且从表面延伸到结构的深度 使得成型材料通过毛细吸引而穿透基板（1）。