公开(公告)号：US08624372B2

公开(公告)日：2014-01-07

申请号：US11466279

申请日：2006-08-22

申请人： Wolfgang Hetzel ,  Jochen Thomas ,  Peter Weitz ,  Ingo Wennemuth

发明人： Wolfgang Hetzel ,  Jochen Thomas ,  Peter Weitz ,  Ingo Wennemuth

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

摘要翻译： 半导体部件（10）具有作为半导体部件堆叠（25）的堆叠元件的插入基板（1）。 所述插入器基板（1）在所述插入器基板侧（2,4）中的一个上具有在其侧边缘（22）中被塑料组合物（12）保护的半导体芯片。 在与半导体芯片（6）相对的插入器侧（2,4）上布置有由塑料组合物（12）部分覆盖的插入件结构（3）。 插入器基板（1）的边缘区域（11）保持不含任何塑料组合物（12），并且在两个插入件侧（2,4）上通过接触件彼此电连接的外部接触焊盘（7） 8）。

公开(公告)号：US08072085B2

公开(公告)日：2011-12-06

申请号：US10577173

申请日：2004-10-25

申请人： Wolfgang Hetzel ,  Jochen Thomas

发明人： Wolfgang Hetzel ,  Jochen Thomas

IPC分类号： H01L23/28 ,  H01L23/29 ,  H01L23/495

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.

摘要翻译： 公开了一种具有塑料封装模塑料，半导体芯片和引线框架的半导体器件。 在一个实施例中，将半导体芯片嵌入塑料封装模塑料中。 半导体芯片的上侧和塑料封装模塑料被布置在引线框架上。 在引线框架和具有半导体芯片的塑料封装模制化合物之间布置有用于上部区域与半导体器件的下部区域的机械去耦的弹性粘合剂层。

公开(公告)号：US07948071B2

公开(公告)日：2011-05-24

申请号：US12116079

申请日：2008-05-06

申请人： Jochen Thomas ,  Peter Weitz ,  Jurgen Grafe ,  Harry Hedler ,  Jens Pohl

发明人： Jochen Thomas ,  Peter Weitz ,  Jurgen Grafe ,  Harry Hedler ,  Jens Pohl

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

摘要： An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.

摘要翻译： 堆叠式模具组件的装置和制造方法。 第一管芯被放置在衬底上，使得管芯的背面，即与接合焊盘的侧面相反的一侧，优选地通过粘合剂耦合到衬底。 引线将第一管芯的接合焊盘电耦合到衬底上的接触点。 第二管芯被放置在第一管芯上，引线将第二管芯的接合焊盘电耦合到衬底上的接触点。 优选地，间隔件被放置在第一管芯和第二管芯之间。 另外的模具可以堆叠在第二模具上。

公开(公告)号：US20100032817A1

公开(公告)日：2010-02-11

申请号：US10577173

申请日：2004-10-25

申请人： Wolfgang Hetzel ,  Jochen Thomas

发明人： Wolfgang Hetzel ,  Jochen Thomas

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.

摘要翻译： 公开了一种具有塑料封装模塑料，半导体芯片和引线框架的半导体器件。 在一个实施例中，将半导体芯片嵌入塑料封装模塑料中。 半导体芯片的上侧和塑料封装模塑料被布置在引线框架上。 在引线框架和具有半导体芯片的塑料封装模制化合物之间布置有用于上部区域与半导体器件的下部区域的机械去耦的弹性粘合剂层。

公开(公告)号：US20080203581A1

公开(公告)日：2008-08-28

申请号：US11679594

申请日：2007-02-27

申请人： Jochen Thomas ,  Wolfgang Hetzel ,  Mathias Grumm

发明人： Jochen Thomas ,  Wolfgang Hetzel ,  Mathias Grumm

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal path being coupled to the first signal path, and a second substrate on the second interface layer. In one embodiment, the second substrate includes an electronic device, the electronic device being coupled to the second signal path of the second interface layer.

摘要翻译： 公开了一种集成电路。 在一个实施例中，集成电路包括在第一基板上的第一接口层，第一接口层包括第一信号路径，第一接口层上的第二接口层，第二接口层包括第二信号路径，第二信号 路径耦合到第一信号路径，第二基板在第二接口层上。 在一个实施例中，第二基板包括电子设备，电子设备耦合到第二接口层的第二信号路径。

公开(公告)号：US07352057B2

公开(公告)日：2008-04-01

申请号：US11245920

申请日：2005-10-07

申请人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

发明人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L24/48 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

摘要翻译： 公开了一种在布线基板上具有内部半导体芯片堆叠的半导体模块。 在一个实施例中，半导体芯片堆叠具有被布置成偏移的半导体芯片，半导体芯片具有在其有源顶侧的至少一个边缘区域中的接合连接焊盘。 这些接合连接焊盘通过接合连接电连接到布线基板。 在这种情况下，半导体芯片以偏移的方式堆叠在彼此的顶部，使得接合连接焊盘保持没有层叠在其上的半导体芯片。 在这种情况下，半导体芯片可以是与在不同边缘区域中的中心布置的接触区域的布线结构方面可能不同的例如成对的硅芯片。

公开(公告)号：US20070158815A1

公开(公告)日：2007-07-12

申请号：US10552046

申请日：2004-04-02

申请人： Fung Chen ,  Seong Kwang Kim ,  Wee Cha ,  Yi-Sheng Sun ,  Wolfgang Hetzel ,  Jochen Thomas

发明人： Fung Chen ,  Seong Kwang Kim ,  Wee Cha ,  Yi-Sheng Sun ,  Wolfgang Hetzel ,  Jochen Thomas

IPC分类号： H01L23/48

CPC分类号： H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

摘要翻译： 公开了一种BGA封装，其包括具有基底基板的基底IC结构，其开口沿着贯穿的方向延伸。 第一半导体芯片正面朝下地安装在基底基板上，使得其接合焊盘可通过开口接近。 该封装还包括一个次级IC结构，该二级IC结构包括一个具有在其上延伸的开口的次级衬底和一个第二半导体芯片。 第二芯片正面朝下安装在二次基板上，使得其接合焊盘可通过次级基板中的开口接近。 密封剂填充次级基底中的开口并且在次级基底的下侧上形成基本平坦的表面。 基本平坦的表面通过粘合剂安装到基底IC结构的第一芯片上。 导线将次级IC结构的导电部分连接到基极IC结构的导电部分。

公开(公告)号：US07198979B2

公开(公告)日：2007-04-03

申请号：US10701742

申请日：2003-11-04

申请人： Jochen Thomas ,  Wolfgang Hetzel ,  Ingo Wennemuth

发明人： Jochen Thomas ,  Wolfgang Hetzel ,  Ingo Wennemuth

IPC分类号： H01L21/00 ,  H01L21/46 ,  H01L21/44 ,  H01L23/02 ,  H01L29/40

CPC分类号： H01L23/3157 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

摘要翻译： 堆叠半导体芯片的方法包括提供四个半导体芯片，每个半导体芯片包括具有中心焊盘的顶表面。 每个接合焊盘通过导电层电耦合到位于半导体芯片的周边部分中的第二接合焊盘。 第一和第二半导体芯片彼此并排地布置在载体衬底上。 来自第一和第二半导体芯片的第二接合焊盘被结合到衬底上的相应的着陆焊盘。 然后将第三半导体芯片堆叠在第二半导体芯片上方的第一半导体芯片和第四半导体芯片上。 然后可以将第三和第四半导体芯片的第二接合焊盘接合到衬底的接触焊盘。 然后可以将衬底分离成包括第一和第三半导体芯片的第一堆叠以及包括第二和第四半导体芯片的第二堆叠。

公开(公告)号：US20060091518A1

公开(公告)日：2006-05-04

申请号：US11245920

申请日：2005-10-07

申请人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

发明人： Jurgen Grafe ,  Sylke Ludewig ,  Jochen Thomas ,  Peter Weitz

IPC分类号： H01L23/02

CPC分类号： H01L24/48 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

摘要翻译： 公开了一种在布线基板上具有内部半导体芯片堆叠的半导体模块。 在一个实施例中，半导体芯片堆叠具有被布置成偏移的半导体芯片，半导体芯片具有在其有源顶侧的至少一个边缘区域中的接合连接焊盘。 这些接合连接焊盘通过接合连接电连接到布线基板。 在这种情况下，半导体芯片以偏移的方式堆叠在彼此的顶部，使得接合连接焊盘保持没有层叠在其上的半导体芯片。 在这种情况下，半导体芯片可以是与在不同边缘区域中的中心布置的接触区域的布线结构方面可能不同的例如成对的硅芯片。

公开(公告)号：US06894381B2

公开(公告)日：2005-05-17

申请号：US10738071

申请日：2003-12-17

申请人： Wolfgang Hetzel ,  Anton Legen ,  Jochen Thomas

发明人： Wolfgang Hetzel ,  Anton Legen ,  Jochen Thomas

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/02

CPC分类号： H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： The invention relates to an electronic device having a stack of semiconductor chips, and to a method for the production thereof. A first semiconductor chip is arranged on a rewiring substrate, and at least one semiconductor stack chip is arranged on the first semiconductor chip. A rewiring plane is arranged between the semiconductor chips. The contact areas of the semiconductor chips are connected to external contacts of the device by the rewiring plane and the rewiring substrate.

摘要翻译： 本发明涉及一种具有半导体芯片堆叠的电子设备及其生产方法。 第一半导体芯片布置在重新布线基板上，并且至少一个半导体堆叠芯片布置在第一半导体芯片上。 半导体芯片之间布置有重新布线平面。 半导体芯片的接触区域通过重新布线平面和重新布线基板连接到器件的外部触点。