摘要:
An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.
摘要:
Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.
摘要:
The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.
摘要:
A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word lines or bit lines which are to be completely repaired, these addresses are referred to as second fault addresses. If the first fault address corresponds to the second fault address, the first fault address is deleted and not further processed. In a second comparison, it is determined, by reference to the number of non-deleted first fault addresses, whether an address of a word line or bit line is used as a new second fault address for the first comparison method. The number of addresses of faulty memory cells are thus reduced.
摘要:
The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.
摘要:
A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.
摘要:
The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting data stored in the semiconductor memory apparatus, at least one phase adjustment device which is designed for approximately adjusting a phase of the data read clock signal on the basis of a phase of the external clock signal at least one phase difference test device which is designed for approximately detecting a phase difference between the phase of the data read clock signal and the phase of the external clock signal and for outputting a test result on the basis of the detected phase difference.
摘要:
The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.
摘要:
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
摘要:
The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.