公开(公告)号：US06910161B2

公开(公告)日：2005-06-21

申请号：US10016863

申请日：2001-12-14

申请人： Justus Kuhn ,  Peter Weitz

发明人： Justus Kuhn ,  Peter Weitz

IPC分类号： G11C29/00 ,  G11C16/06

CPC分类号： G11C29/72 ,  G11C29/814

摘要： A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word lines or bit lines which are to be completely repaired, these addresses are referred to as second fault addresses. If the first fault address corresponds to the second fault address, the first fault address is deleted and not further processed. In a second comparison, it is determined, by reference to the number of non-deleted first fault addresses, whether an address of a word line or bit line is used as a new second fault address for the first comparison method. The number of addresses of faulty memory cells are thus reduced.

摘要翻译： 用于减少故障存储器单元的地址的方法和设备将故障存储器单元的地址作为第一故障地址与待完全修复的字线或位线的地址进行比较，这些地址被称为第二故障地址。 如果第一个故障地址对应于第二个故障地址，则第一个故障地址被删除，而不进一步处理。 在第二比较中，通过参照未删除的第一故障地址的数量，确定字线或位线的地址是否用作第一比较方法的新的第二故障地址。 因此，故障存储器单元的地址数量减少。

公开(公告)号：US06865707B2

公开(公告)日：2005-03-08

申请号：US10109657

申请日：2002-04-01

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Luepke ,  Jochen Mueller ,  Peter Poechmueller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Luepke ,  Jochen Mueller ,  Peter Poechmueller ,  Michael Schittenhelm

IPC分类号： G01R31/3183 ,  G11C29/14 ,  G11C29/36 ,  G01R31/28 ,  G06F11/00

CPC分类号： G11C29/14 ,  G01R31/3183 ,  G11C29/36

摘要： Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received by a test unit with a specific clock frequency multiplication factor. Also provided is a plurality of data registers for storing test data words read from the data registers, and multiplexer that switches through a test data word read from a data register with the high clock frequency of the output clock signal to a data bus in a way dependent on a register selection control datum of a multi-position register selection control data vector.

摘要翻译： 用于产生用于测试具有倍频电路的电路的测试数据模式的测试数据发生器，其增加由测试单元以特定时钟倍频因子接收的输入时钟信号的低时钟频率。 还提供了多个数据寄存器，用于存储从数据寄存器读取的测试数据字，以及多路复用器，以一种方式将通过从输出时钟信号的高时钟频率从数据寄存器读取的测试数据字切换到数据总线 取决于多位置寄存器选择控制数据向量的寄存器选择控制基准。

公开(公告)号：US06556492B2

公开(公告)日：2003-04-29

申请号：US09907695

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： G11C700

CPC分类号： G11C29/56

摘要： The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

公开(公告)号：US06721904B2

公开(公告)日：2004-04-13

申请号：US09907693

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： H02H305

CPC分类号： G11C29/12015 ,  G11C29/48 ,  G11C29/56012

摘要： The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

摘要翻译： 本发明涉及一种用于测试快速集成数字电路，特别是半导体模块（例如SDRAM）的系统。 为了在DDR-SDRAM的测试中实现必要的按时间顺序的精度，同时大规模生产所需的测试系统的高度并行性，将额外的半导体电路模块（BOST模块）插入到信号中 标准测试设备和要测试的SDRAM之间的路径。 该附加模块被设置为乘以常规测试设备的相对较慢的时钟频率，并且根据测试信号来确定用于测试SDRAM模块的控制信号，地址和数据背景的信号序列 设备以及在测试前编程的寄存器内容，在BOST模块中。

公开(公告)号：US07062690B2

公开(公告)日：2006-06-13

申请号：US09907786

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G01R31/31905 ,  G11C29/56

摘要： A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

公开(公告)号：US20060064620A1

公开(公告)日：2006-03-23

申请号：US11227714

申请日：2005-09-15

申请人： Justus Kuhn ,  Wolfgang Spirkl

发明人： Justus Kuhn ,  Wolfgang Spirkl

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/028 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50012

摘要： The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting data stored in the semiconductor memory apparatus, at least one phase adjustment device which is designed for approximately adjusting a phase of the data read clock signal on the basis of a phase of the external clock signal at least one phase difference test device which is designed for approximately detecting a phase difference between the phase of the data read clock signal and the phase of the external clock signal and for outputting a test result on the basis of the detected phase difference.

摘要翻译： 本发明涉及具有用于输入外部时钟信号的至少一个时钟输入触点的半导体存储装置，至少一个时钟输出触点，用于输出用于读取存储在半导体存储装置中的数据的数据读取时钟信号，至少一个数据触点 用于输出存储在所述半导体存储装置中的数据，所述至少一个相位调整装置被设计为基于所述外部时钟信号的相位近似地调整所述数据读取时钟信号的相位，所述至少一个相位差测试装置是 设计用于近似地检测数据读时钟信号的相位与外部时钟信号的相位之间的相位差，并且用于基于检测到的相位差输出测试结果。

公开(公告)号：US06862702B2

公开(公告)日：2005-03-01

申请号：US09907776

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： G11C29/56 ,  G11C29/00

CPC分类号： G11C29/56

摘要： The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

摘要翻译： 新颖的地址计数器可以与用于测试数字电路的现有测试单元结合使用 - 用于寻址同步高频数字电路，特别是快速存储器件。 在可编程偏移寄存器中提供地址偏移值，其中多路复用器电路和选择和组合电路基于由测试单元以低频和并联馈送的输入信号。 可以以非常灵活的方式在高时钟频率下实现简单的地址改变和地址跳转。

公开(公告)号：US06853206B2

公开(公告)日：2005-02-08

申请号：US10736356

申请日：2003-12-15

申请人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter P{hacek over (o)}chmüller ,  Jürgen Weidenhöfer

发明人： Michael Hübner ,  Gunnar Krause ,  Justus Kuhn ,  Jochen Müller ,  Peter P{hacek over (o)}chmüller ,  Jürgen Weidenhöfer

IPC分类号： G01R31/3185 ,  G01R31/319 ,  G11C29/00 ,  G11C29/48 ,  G01R31/02 ,  G01R31/28

CPC分类号： G01R31/319 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G11C29/006 ,  G11C29/48

摘要： A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

摘要翻译： 用于同时测试位于晶片上的多个集成电路，特别是快速半导体存储器模块的测试配置。 测试配置包括用于提升属于测试系统的电信号线的承载板，用于产生与要测试的电路上的接触区域的电连接的接触针，以及布置在承载板上的多个有源模块 。 有源模块分别被分配给要并联测试的电路之一，并且每一个都被插入测试系统和要测试的相关电路之间的信号路径中。 在优选实施例中，有源模块基于与载板的平面成直角的方向至少部分地重叠布置。

公开(公告)号：US07117403B2

公开(公告)日：2006-10-03

申请号：US09907777

申请日：2001-07-18

申请人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

发明人： Wolfgang Ernst ,  Gunnar Krause ,  Justus Kuhn ,  Jens Lüpke ,  Jochen Müller ,  Peter Pöchmüller ,  Michael Schittenhelm

IPC分类号： G11C29/00 ,  G06F11/00 ,  G01R31/28

CPC分类号： G11C29/10 ,  G01R31/3183

摘要： The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

公开(公告)号：US07043653B2

公开(公告)日：2006-05-09

申请号：US10215228

申请日：2002-08-08

申请人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

发明人： Justus Kuhn ,  Hermann Ruckerbauer ,  Frank Thiele

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

摘要翻译： 将接收信号的逻辑/存储器组件的内部时钟信号作为参考时钟发送到发送逻辑/存储器组件。 借助于参考时钟，产生发送逻辑/存储器部件的输出单元的传输时钟，使得发送的信号与该部件的内部时钟信号同步到达接收部件的接收单元。