公开(公告)号：US06436302B1

公开(公告)日：2002-08-20

申请号：US09492267

申请日：2000-01-27

申请人： Juy-Lung Li ,  Tse-Yong Yao ,  Fred C. Redeker ,  Rajeev Bajaj ,  Yutao Ma

发明人： Juy-Lung Li ,  Tse-Yong Yao ,  Fred C. Redeker ,  Rajeev Bajaj ,  Yutao Ma

IPC分类号： H01L21463

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/3212

摘要： Cu metallization is treated to reduce defects and effect passivation, and to reduce leakage between lines, by removing surface defects subsequent to CMP and barrier layer removal. Embodiments include the sequential steps of: CMP and barrier layer removal; buffing with a solution comprising citric acid, ammonium hydroxide and deionized water to remove copper oxide; rinsing with deionized water or an inhibitor solution, e.g., benzotriazole or 5-methyl triazole in deionized water; buffing with an abrasive slurry; and rinsing with deionized water or an inhibitor solution.

摘要翻译： 处理Cu金属化以减少缺陷并实现钝化，并通过去除CMP和阻挡层去除之后的表面缺陷来减少线之间的泄漏。 实施例包括顺序步骤：CMP和阻挡层去除; 用包含柠檬酸，氢氧化铵和去离子水的溶液抛光以除去氧化铜; 用去离子水或抑制剂溶液（例如苯并三唑或5-甲基三唑）在去离子水中冲洗; 用磨料浆抛光; 并用去离子水或抑制剂溶液冲洗。

公开(公告)号：US06436832B1

公开(公告)日：2002-08-20

申请号：US09578157

申请日：2000-05-23

申请人： Yutao Ma ,  Juilung Li ,  Fred C. Redeker ,  Tse-Yong Yao ,  Rajeev Bajaj

发明人： Yutao Ma ,  Juilung Li ,  Fred C. Redeker ,  Tse-Yong Yao ,  Rajeev Bajaj

IPC分类号： H01L2100

CPC分类号： H01L21/02074 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/3212

摘要： High through-put CMP is achieved by the application of a cleaning composition on to an exposed surface of a metal layer prior to polishing the bulk metal layer. Embodiments of the present invention include applying an aqueous composition containing citric acid and ammonium hydroxide in deionized water to remove a native oxide film that forms on a copper containing layer and then polishing the copper containing layer to substantially planarize the metal layer.

摘要翻译： 在抛光本体金属层之前，通过将清洁组合物施加到金属层的暴露表面上来实现高通量CMP。 本发明的实施方案包括将含有柠檬酸和氢氧化铵的水性组合物施加到去离子水中以除去在含铜层上形成的自然氧化物膜，然后抛光含铜层以使金属层基本上平坦化。

公开(公告)号：US06620027B2

公开(公告)日：2003-09-16

申请号：US10044379

申请日：2002-01-09

申请人： Ajoy Zutshi ,  Rajeev Bajaj ,  Fred C. Redeker ,  Yutao Ma ,  Kapila Wijekoon

发明人： Ajoy Zutshi ,  Rajeev Bajaj ,  Fred C. Redeker ,  Yutao Ma ,  Kapila Wijekoon

IPC分类号： B24B5100

CPC分类号： B24B37/12 ,  B24B37/042 ,  B24B37/24

摘要： Methods and apparatus for planarizing a substrate surface having copper containing materials thereon is provided. In one aspect, the invention provides a system for processing substrates comprising a first platen adapted for polishing a substrate with a hard polishing pad disposed on the first platen, a second platen adapted for polishing a substrate with a hard polishing pad disposed on the second platen, and a third platen adapted for polishing a substrate with a hard polishing pad disposed on the third platen. In another aspect, the invention provides a method for planarizing a substrate surface by the system described above including substantially removing bulk copper containing materials on the first platen, removing residual copper containing materials on the second platen, and then removing a barrier layer on the third platen. A computer readable program may also be provided for performing the methods described herein.

公开(公告)号：US06261157B1

公开(公告)日：2001-07-17

申请号：US09318225

申请日：1999-05-25

申请人： Rajeev Bajaj ,  Fritz C. Redeker ,  John M. White ,  Shijian Li ,  Yutao Ma

发明人： Rajeev Bajaj ,  Fritz C. Redeker ,  John M. White ,  Shijian Li ,  Yutao Ma

IPC分类号： B24B722

CPC分类号： B24B37/345 ,  B24B27/0023 ,  H01L21/02074 ,  H01L21/3212

摘要： A selective Damascene chemical mechanical polishing (CMP) technique is used to planarize a semiconductor device to remove surface topography. The semiconductor device includes a semiconductor layer formed on a substrate, an insulating layer formed over the semiconductor layer and patterned to expose a portion of the semiconductor layer, a barrier layer formed over the insulating layer and the exposed portion of the semiconductor layer, and an electrically conductive layer formed over the barrier layer. The semiconductor device is pressed against a first rotating polishing pad that has no embedded abrasive particles to remove a portion of the conductive layer that overlies both the barrier layer and the insulating layer. The semiconductor device is then pressed against a second rotating polishing pad that has embedded abrasive particles to expose a portion of the barrier layer that overlies the insulating layer. The device is then pressed against a third rotating polishing pad that has no embedded abrasive particles to remove the portion of the barrier layer that overlies the insulating layer.

摘要翻译： 使用选择性的大马士革化学机械抛光（CMP）技术来平面化半导体器件以去除表面形貌。 半导体器件包括形成在衬底上的半导体层，形成在半导体层上并被图案化以暴露半导体层的一部分的绝缘层，形成在绝缘层上的阻挡层和半导体层的暴露部分， 形成在阻挡层上的导电层。 半导体器件被压在没有嵌入的磨料颗粒的第一旋转抛光垫上，以去除覆盖阻挡层和绝缘层两者的导电层的一部分。 然后将半导体器件压在具有嵌入的磨料颗粒的第二旋转抛光垫上，以暴露位于绝缘层上的阻挡层的一部分。 然后将装置压在没有嵌入的磨料颗粒的第三旋转抛光垫上，以去除覆盖在绝缘层上的阻挡层的部分。

公开(公告)号：US20090119085A1

公开(公告)日：2009-05-07

申请号：US11935969

申请日：2007-11-06

申请人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

发明人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

摘要翻译： 公开了用于建模晶体管的动态行为的方法和系统。 该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算 根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压 根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

公开(公告)号：US07933747B2

公开(公告)日：2011-04-26

申请号：US11935969

申请日：2007-11-06

申请人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

发明人： Yutao Ma ,  Min-Chie Jeng ,  Bruce W. McGaughy ,  Lifeng Wu ,  Zhihong Liu

IPC分类号： G06F17/10

CPC分类号： G06F17/5036

摘要： Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.

摘要翻译： 公开了用于建模晶体管的动态行为的方法和系统。 该方法包括使用查找表来表示晶体管的静态特性，从查找表中选择晶体管的实例以建模晶体管的动态行为，使用非准静态分析模型计算实例的先前状态，计算 根据时间变化率计算实例的信道电荷的变化，使用先前状态计算实例的当前状态和信道电荷的变化，计算修改的终端电压，该电压包括两端的寄生电阻两端的动态电压 根据当前状态和实例的先前状态，晶体管的端子，并将修改的端子电压存储在用于对当前状态下的晶体管的动态行为进行建模的存储器件中。

公开(公告)号：US07979814B1

公开(公告)日：2011-07-12

申请号：US12047222

申请日：2008-03-12

申请人： Yutao Ma ,  Yi Xu

发明人： Yutao Ma ,  Yi Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06T17/00 ,  G06T2200/28

摘要： Model evaluation and circuit simulation/verification is performed in a graphical processing unit (GPU). A multitude of first texture data corresponding to size parameters of devices are stored. A multitude of second texture data corresponding to instance parameters of the devices are stored. A multitude of third texture data corresponding to models of the devices are stored. A multitude of fourth texture data corresponding to terminal voltages received by the device are stored. A multitude of links linking each device instance to an associated device model, size parameters and instance parameters are stored. A quad having a size defined by the multitude of links is drawn by the quad in the GPU. Each thread in the quad is assigned to a different one of the multitude of links. The computations are carried out in each thread using the linked data to perform the model evaluation.

摘要翻译： 在图形处理单元（GPU）中执行模型评估和电路仿真/验证。 存储对应于设备的大小参数的多个第一纹理数据。 存储对应于设备的实例参数的多个第二纹理数据。 存储与设备的模型相对应的多个第三纹理数据。 存储对应于由设备接收的端子电压的多个第四纹理数据。 将每个设备实例链接到相关设备模型，大小参数和实例参数的多个链接被存储。 具有由多个链接定义的大小的四边形由GPU中的四边形绘制。 四角形中的每个线程都分配给多个链接中的一个。 使用链接的数据在每个线程中执行计算以执行模型评估。

公开(公告)号：US07815495B2

公开(公告)日：2010-10-19

申请号：US11734063

申请日：2007-04-11

申请人： Kun Xu ,  Jimin Zhang ,  James C. Wang ,  Thomas H. Osterheld ,  Yutao Ma ,  Steven M. Zuniga ,  Jin Yi

发明人： Kun Xu ,  Jimin Zhang ,  James C. Wang ,  Thomas H. Osterheld ,  Yutao Ma ,  Steven M. Zuniga ,  Jin Yi

IPC分类号： B24B53/12

CPC分类号： B24B53/017 ,  B24B29/005 ,  B24B53/12

摘要： A pad conditioner is provided for conditioning a polishing pad in chemical mechanical planarization (CMP). The pad conditioner comprises a plastic abrasive portion having a first hardness and optionally a brush portion having a second hardness less than the first hardness. The plastic abrasive portion comprises a base plate and a plurality of plastic nodules formed on a surface of the base plate, each of the plastic nodules having a planar top surface, wherein the planar top surface is positioned to substantially contact a polishing pad. The brush portion may be positioned adjacent to the plastic abrasive portion, the brush portion having a plurality of brush elements positioned to substantially contact the pad.

摘要翻译： 提供了用于在化学机械平面化（CMP）中调理抛光垫的衬垫调节器。 衬垫调节剂包括具有第一硬度的塑料磨料部分和任选地具有小于第一硬度的第二硬度的刷部分。 塑料研磨部分包括基板和形成在基板的表面上的多个塑料结节，每个塑料结节具有平坦的顶表面，其中平面顶表面被定位成基本接触抛光垫。 刷部分可以定位成与塑料研磨部分相邻，刷部分具有多个刷子元件，其定位成基本上接触焊盘。

公开(公告)号：US20050177807A1

公开(公告)日：2005-08-11

申请号：US10773541

申请日：2004-02-06

申请人： Yutao Ma ,  Bruce McGaughy ,  Zhihong Liu

发明人： Yutao Ma ,  Bruce McGaughy ,  Zhihong Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.

摘要翻译： 本发明包括一种在电路仿真期间检测模型冲压误差而不需要黄金数据的方法。 该方法通过确定模型冲压矩阵中的条目是否在解决电路方程之前根据多个预设规则相互关联来检查模型冲压误差。

公开(公告)号：US5346747A

公开(公告)日：1994-09-13

申请号：US996651

申请日：1992-12-24

申请人： Vincent M. Vancho ,  Hak H. Wu ,  Yutao Ma ,  Erik L. Jorgensen

发明人： Vincent M. Vancho ,  Hak H. Wu ,  Yutao Ma ,  Erik L. Jorgensen

IPC分类号： B32B15/08 ,  C08J5/04 ,  D01F6/62 ,  D04H3/00 ,  D21H13/24 ,  H05K1/03 ,  B32B9/00

CPC分类号： H05K1/0366 ,  C08J5/04 ,  H05K2201/0141 ,  H05K2201/0145 ,  H05K2201/0278 ,  H05K2201/0293 ,  Y10S428/901 ,  Y10T428/24917

摘要： Composite printed circuit board substrates having fiber reinforcement in a polymer matrix are disclosed. The fibers may be thermotropic melt processable liquid crystal polymer fibers.

摘要翻译： 公开了在聚合物基体中具有纤维增强的复合印刷电路板基板。 纤维可以是热致熔融加工的液晶聚合物纤维。