公开(公告)号：US06297168B1

公开(公告)日：2001-10-02

申请号：US09677068

申请日：2000-09-29

申请人： Jyu-Horng Shieh ,  Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chi Chao ,  Chia-Shia Tsai

发明人： Jyu-Horng Shieh ,  Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chi Chao ,  Chia-Shia Tsai

IPC分类号： H01L213065

CPC分类号： H01L21/7681 ,  H01L21/31116

摘要： Within a method for etching a trench within a silicon oxide layer there is first provided a substrate. There is then formed over the substrate a silicon oxide layer. There is then formed over the silicon oxide layer a masking layer. There is then etched, while employing a plasma etch method in conjunction with the masking layer as an etch mask layer, the silicon oxide layer to form an etched silicon oxide layer defining a trench. Within the method, the plasma etch method employs an etchant gas composition comprising: (1) octafluorocyclobutane; and (2) at least one of carbon tetrafluoride, difluoromethane, hexafluoroethane and oxygen; but excluding (3) a carbon and oxygen containing gas.

摘要翻译： 在氧化硅层内蚀刻沟槽的方法中，首先提供衬底。 然后在衬底上形成氧化硅层。 然后在氧化硅层上形成掩模层。 然后蚀刻，同时使用等离子体蚀刻方法结合掩模层作为蚀刻掩模层，氧化硅层形成蚀刻氧化硅层，限定沟槽。 在该方法中，等离子体蚀刻方法采用蚀刻剂气体组合物，其包含：（1）八氟环丁烷; 和（2）四氟化碳，二氟甲烷，六氟乙烷和氧中的至少一种; 但不包括（3）含碳和含氧气体。

公开(公告)号：US06790770B2

公开(公告)日：2004-09-14

申请号：US10035690

申请日：2001-11-08

申请人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh

发明人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method if provided for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer in subsequent lithographic patterning and RIE etching processes to form a trench opening formed substantially over the via opening.

摘要翻译： 如果提供用于通过在通孔开口中形成树脂塞以改善来自低k IMD层的含氮物质的扩散的方法，以在随后的平版印刷图案化和RIE蚀刻工艺中形成二维镶嵌工艺中的光刻图案化方法 沟槽开口基本上形成在通孔开口上方。

公开(公告)号：US06383943B1

公开(公告)日：2002-05-07

申请号：US09687160

申请日：2000-10-16

申请人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

发明人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

IPC分类号： H01L21302

CPC分类号： H01L21/76843 ,  H01L21/3105 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer then overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer. This is followed by a second anisotropic etch step to remove the etch stop layer not protected by the IMD layer resulting in the formation a notch at the bottom of the via hole. An important step of the present invention is the elimination of this notch accomplished by nitridizing the surface of the IMD layer. A wet polymer cleaning is performed to remove the nitridized IMD surface and eliminating the notch. A glue layer is conformally applied lining the via hole. A second conductive layer is then deposited and the surface is planarized.

摘要翻译： 一种用于消除与在氮化硅蚀刻停止层中由凹口产生的通孔底部的胶层不连续沉积相关的问题的方法。 图案化第一导电层迹线，并且覆盖第一导电层提供氮化硅（SiN）蚀刻停止层。 金属间电介质（IMD）层然后覆盖整个表面。 进行各向异性蚀刻，留下IMD层中的通孔。 然后进行第二个各向异性蚀刻步骤以去除不被IMD层保护的蚀刻停止层，从而在通孔的底部形成切口。 本发明的重要步骤是消除通过使IMD层的表面氮化而实现的这个缺口。 执行湿式聚合物清洁以除去氮化的IMD表面并消除凹口。 粘合层适用于衬套通孔。 然后沉积第二导电层并且将表面平坦化。

公开(公告)号：US06995085B2

公开(公告)日：2006-02-07

申请号：US10346384

申请日：2003-01-17

申请人： Lawrence Lui ,  Chia-Shia Tsai ,  Chao-Cheng Chen ,  Jen-Cheng Liu

发明人： Lawrence Lui ,  Chia-Shia Tsai ,  Chao-Cheng Chen ,  Jen-Cheng Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.

摘要翻译： 一种在双镶嵌沟槽中保护底层扩散阻挡层的方法，以及通过蚀刻工艺与负性光致抗蚀剂的涂层。 双镶嵌工艺从金属间电介质（IMD）层中的通孔蚀刻开始。 接下来，沉积和图案化薄膜阻挡层以填充通孔的底部。 关键的工艺步骤是负性光致抗蚀剂的涂层，其被暴露和显影以部分填充通孔。 通孔中的这种厚的负光致抗蚀剂层保护了薄的扩散阻挡层免于后续的双镶嵌蚀刻加工。

公开(公告)号：US06309962B1

公开(公告)日：2001-10-30

申请号：US09396516

申请日：1999-09-15

申请人： Chao-Cheng Chen ,  Li-Chi Chao ,  Jen-Cheng Liu ,  Min-Huei Lui ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Li-Chi Chao ,  Jen-Cheng Liu ,  Min-Huei Lui ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/76813

摘要： A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.

摘要翻译： 描述了在电介质，特别是低k有机电介质中形成双镶嵌腔的工艺。 电介质由两层由蚀刻停止层隔开组成。 通过使用由两层氧氮化硅分离的氧化硅层组成的硬掩模来实现镶嵌腔的形成。 对于沟槽第一和通过第一方法，仅使用上部氧氮化硅层作为掩模形成第一腔体。 因此，当第二部分被图案化时，由于所述上层相对较薄，所以几乎不发生不对准。 另外的蚀刻步骤导致空腔和沟槽部分延伸到位于电介质层之间的蚀刻停止层的尽可能深。 光致抗蚀剂的最终去除是在硬掩模仍然存在的情况下发生的，因此不会损害有机电介质。 最终蚀刻步骤然后完成该过程。

公开(公告)号：US06211063B1

公开(公告)日：2001-04-03

申请号：US09318020

申请日：1999-05-25

申请人： Jen-Cheng Liu ,  Chia-Shia Tsai

发明人： Jen-Cheng Liu ,  Chia-Shia Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76835

摘要： A method to form dual damascene structures is described. A first silicon oxynitride layer is deposited overlying a provided substrate. A silicate glass layer is deposited overlying the first silicon oxynitride. A second silicon oxynitride layer is deposited overlying the silicate glass. Photoresist is deposited overlying the second silicon oxynitride and is etched to define areas of planned lower trenches. The second silicon oxynitride layer is etched to expose the top surface of the silicate glass layer. The remaining photoresist layer is etched away. An hydrogen silsesquioxane layer is deposited overlying the second silicon oxynitride and the silicate glass. An oxide layer is deposited overlying the hydrogen silsesquioxane. Photoresist is deposited overlying the oxide and is etched to define areas of planned upper trenches. The oxide layer and the hydrogen silsesquioxane layer are etched by reactive ion etching by a recipe comprising C4F8, CO, Ar, and N2 gases to form the upper trenches. The second silicon oxynitride acts as an etch stop. The silicate glass is etched by reactive ion etching by a recipe comprising C4F8, CO, and Ar gases to form the lower trenches. The first silicon oxynitride acts as an etch stop. A metal layer is deposited filling the trenches. The metal layer is etched back to the top surface of the oxide.

摘要翻译： 描述了形成双镶嵌结构的方法。 第一氧氮化硅层沉积在所提供的衬底上。 沉积覆盖第一氮氧化硅的硅酸盐玻璃层。 第二硅氮化硅层沉积在硅酸盐玻璃上。 光刻胶沉积在第二硅氮氧化物上，并被蚀刻以限定计划中的下沟槽的区域。 蚀刻第二氮氧化硅层以暴露硅酸盐玻璃层的顶表面。 残留的光致抗蚀剂层被蚀刻掉。 沉积在第二氮氧化硅和硅酸盐玻璃上的氢倍半硅氧烷层。 沉积在氢倍半硅氧烷上的氧化物层。 光刻胶沉积在氧化物上并被蚀刻以限定计划的上沟槽的区域。 通过包括C4F8，CO，Ar和N2气体的配方通过反应离子蚀刻来蚀刻氧化物层和氢倍半硅氧烷层，以形成上部沟槽。 第二氮氧化硅用作蚀刻停止。 通过包括C4F8，CO和Ar气体的配方通过反应离子蚀刻来蚀刻硅酸盐玻璃，以形成下沟槽。 第一氮氧化硅用作蚀刻停止。 沉积填充沟槽的金属层。 金属层被回蚀刻到氧化物的顶表面。

公开(公告)号：US06323121B1

公开(公告)日：2001-11-27

申请号：US09570018

申请日：2000-05-12

申请人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

发明人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

摘要： A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

摘要翻译： 描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。 该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。 该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。 该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤 ，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

公开(公告)号：US06211061B1

公开(公告)日：2001-04-03

申请号：US09431536

申请日：1999-10-29

申请人： Chao-Cheng Chen ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Li-chih Chao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Li-chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first barrier layer, and a hard mask layer is formed on the dielectric layer. The hard mask layer and the dielectric layer are patterned to form a trench. A second barrier layer is formed over the hard mask layer and on the bottom and sidewalls of the trench. A barc layer is formed over the second barrier layer, thereby filling the trench. The barc layer, the second barrier layer, and the dielectric layer are patterned to form a via opening, preferably using a photoresist mask. The barc layer is patterned without faceting the edges of the via opening due to the second barrier layer. The barc layer and the etch mask are removed by the dielectric layer etch. The first barrier layer and the second barrier layer are removed. A third barrier layer is formed on the bottom and sidewalls of the trench, on the sidewalls of the via opening, and on the first metal pattern through the via opening. The trench and the via opening are filled with metal to form a damascene structure.

摘要翻译： 一种在碳基低K材料中形成双镶嵌结构的方法。 该过程开始于提供其上具有第一金属图案的半导体结构，其中第一金属图案在其上具有第一阻挡层。 在第一阻挡层上形成有机电介质层，在电介质层上形成硬掩模层。 图案化硬掩模层和电介质层以形成沟槽。 第二阻挡层形成在硬掩模层之上以及沟槽的底部和侧壁上。 在第二阻挡层上形成棒状层，由此填充沟槽。 将棒状层，第二阻挡层和电介质层图案化以形成通孔，优选使用光致抗蚀剂掩模。 由于第二阻挡层，棒状层被图案化而不使通孔开口的边缘刻划。 通过电介质层蚀刻去除棒状层和蚀刻掩模。 去除第一阻挡层和第二阻挡层。 第三阻挡层形成在沟槽的底部和侧壁上，通孔开口的侧壁上，通过通孔开口形成在第一金属图案上。 沟槽和通孔开口用金属填充以形成镶嵌结构。

公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

摘要翻译： 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

公开(公告)号：US10090349B2

公开(公告)日：2018-10-02

申请号：US13571099

申请日：2012-08-09

申请人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

发明人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC分类号： H01L27/146

摘要： A device includes an image sensor chip having an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit.