公开(公告)号：US06211061B1

公开(公告)日：2001-04-03

申请号：US09431536

申请日：1999-10-29

申请人： Chao-Cheng Chen ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Li-chih Chao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Li-chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first barrier layer, and a hard mask layer is formed on the dielectric layer. The hard mask layer and the dielectric layer are patterned to form a trench. A second barrier layer is formed over the hard mask layer and on the bottom and sidewalls of the trench. A barc layer is formed over the second barrier layer, thereby filling the trench. The barc layer, the second barrier layer, and the dielectric layer are patterned to form a via opening, preferably using a photoresist mask. The barc layer is patterned without faceting the edges of the via opening due to the second barrier layer. The barc layer and the etch mask are removed by the dielectric layer etch. The first barrier layer and the second barrier layer are removed. A third barrier layer is formed on the bottom and sidewalls of the trench, on the sidewalls of the via opening, and on the first metal pattern through the via opening. The trench and the via opening are filled with metal to form a damascene structure.

摘要翻译： 一种在碳基低K材料中形成双镶嵌结构的方法。 该过程开始于提供其上具有第一金属图案的半导体结构，其中第一金属图案在其上具有第一阻挡层。 在第一阻挡层上形成有机电介质层，在电介质层上形成硬掩模层。 图案化硬掩模层和电介质层以形成沟槽。 第二阻挡层形成在硬掩模层之上以及沟槽的底部和侧壁上。 在第二阻挡层上形成棒状层，由此填充沟槽。 将棒状层，第二阻挡层和电介质层图案化以形成通孔，优选使用光致抗蚀剂掩模。 由于第二阻挡层，棒状层被图案化而不使通孔开口的边缘刻划。 通过电介质层蚀刻去除棒状层和蚀刻掩模。 去除第一阻挡层和第二阻挡层。 第三阻挡层形成在沟槽的底部和侧壁上，通孔开口的侧壁上，通过通孔开口形成在第一金属图案上。 沟槽和通孔开口用金属填充以形成镶嵌结构。

公开(公告)号：US06323121B1

公开(公告)日：2001-11-27

申请号：US09570018

申请日：2000-05-12

申请人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

发明人： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

摘要： A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

摘要翻译： 描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。 该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。 该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。 该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤 ，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

摘要翻译： 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

公开(公告)号：US06383943B1

公开(公告)日：2002-05-07

申请号：US09687160

申请日：2000-10-16

申请人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

发明人： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

IPC分类号： H01L21302

CPC分类号： H01L21/76843 ,  H01L21/3105 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer then overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer. This is followed by a second anisotropic etch step to remove the etch stop layer not protected by the IMD layer resulting in the formation a notch at the bottom of the via hole. An important step of the present invention is the elimination of this notch accomplished by nitridizing the surface of the IMD layer. A wet polymer cleaning is performed to remove the nitridized IMD surface and eliminating the notch. A glue layer is conformally applied lining the via hole. A second conductive layer is then deposited and the surface is planarized.

摘要翻译： 一种用于消除与在氮化硅蚀刻停止层中由凹口产生的通孔底部的胶层不连续沉积相关的问题的方法。 图案化第一导电层迹线，并且覆盖第一导电层提供氮化硅（SiN）蚀刻停止层。 金属间电介质（IMD）层然后覆盖整个表面。 进行各向异性蚀刻，留下IMD层中的通孔。 然后进行第二个各向异性蚀刻步骤以去除不被IMD层保护的蚀刻停止层，从而在通孔的底部形成切口。 本发明的重要步骤是消除通过使IMD层的表面氮化而实现的这个缺口。 执行湿式聚合物清洁以除去氮化的IMD表面并消除凹口。 粘合层适用于衬套通孔。 然后沉积第二导电层并且将表面平坦化。

公开(公告)号：US06309962B1

公开(公告)日：2001-10-30

申请号：US09396516

申请日：1999-09-15

申请人： Chao-Cheng Chen ,  Li-Chi Chao ,  Jen-Cheng Liu ,  Min-Huei Lui ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Li-Chi Chao ,  Jen-Cheng Liu ,  Min-Huei Lui ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/76813

摘要： A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.

摘要翻译： 描述了在电介质，特别是低k有机电介质中形成双镶嵌腔的工艺。 电介质由两层由蚀刻停止层隔开组成。 通过使用由两层氧氮化硅分离的氧化硅层组成的硬掩模来实现镶嵌腔的形成。 对于沟槽第一和通过第一方法，仅使用上部氧氮化硅层作为掩模形成第一腔体。 因此，当第二部分被图案化时，由于所述上层相对较薄，所以几乎不发生不对准。 另外的蚀刻步骤导致空腔和沟槽部分延伸到位于电介质层之间的蚀刻停止层的尽可能深。 光致抗蚀剂的最终去除是在硬掩模仍然存在的情况下发生的，因此不会损害有机电介质。 最终蚀刻步骤然后完成该过程。

公开(公告)号：US06743732B1

公开(公告)日：2004-06-01

申请号：US09769812

申请日：2001-01-26

申请人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

发明人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76813

摘要： A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast. The invention's NH3 only etch had a 30 to 80% high etch rate than N2/H2 etches of low-k materials like Silk™.

摘要翻译： 仅使用NH3或NH3 / H2或NH3 / H2气体的有机低k电介质层的等离子体蚀刻工艺。 在衬底上形成低k电介质层。 在低k电介质层上形成掩模图案。 掩模图案具有开口。 使用本发明的蚀刻工艺，使用掩模图案作为蚀刻掩模，通过开口蚀刻低k电介质层。 在第一实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3气体来蚀刻低k电介质层。 在第二实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / H 2气体来蚀刻低k电介质层。 在第三实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / N 2气体来蚀刻低k电介质层。 本发明的含NH 3的等离子体蚀刻意外地快速蚀刻有机低k材料。 本发明的仅NH3蚀刻具有比Silk TM的低k材料的N 2 / H 2蚀刻高30至80％的高蚀刻速率。

公开(公告)号：US06242362B1

公开(公告)日：2001-06-05

申请号：US09366736

申请日：1999-08-04

申请人： Jen-Cheng Liu ,  Huan-Just Lin ,  Chia-Shiung Tsai ,  Yung-Kuan Hsaio

发明人： Jen-Cheng Liu ,  Huan-Just Lin ,  Chia-Shiung Tsai ,  Yung-Kuan Hsaio

IPC分类号： H01L21302

CPC分类号： H01L21/32137 ,  H01L21/32139

摘要： The present invention provides a method of fabricating a vertical hard mask/conductive pattern profile. The process begins by forming a polysilicon or more preferably a polysilicon and silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern using Cl2/He—O2/N2 etch chemistry, thereby forming a hard mask/conductive pattern profile that is vertical.

摘要翻译： 本发明提供了制造垂直硬掩模/导电图案轮廓的方法。 该过程通过在半导体衬底上形成多晶硅或更优选多晶硅和硅化物导电层开始。 在导电层上形成氧氮化硅硬掩模层。 将氮氧化硅硬掩模层图案化以形成硬掩模图案。 使用Cl 2 / He-O 2 / N 2蚀刻化学法将导电层图案化以形成导电图案，从而形成垂直的硬掩模/导电图案轮廓。

公开(公告)号：US06225203B1

公开(公告)日：2001-05-01

申请号：US09304334

申请日：1999-05-03

申请人： Jen-Cheng Liu ,  Jen-Shiang Leu ,  Chia-Shiung Tsai

发明人： Jen-Cheng Liu ,  Jen-Shiang Leu ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L27/10855 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885

摘要： A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

摘要翻译： 描述了在制造自对准接触中具有良好外形的PE-CVD氮化硅间隔物的方法，其中两步蚀刻工艺形成间隔物。 半导体器件结构形成在半导体衬底上。 通过等离子体增强化学气相沉积在衬底的表面上并覆盖半导体器件结构来沉积氮化硅层。 使用两步蚀刻工艺蚀刻掉氮化硅层，以在半导体器件结构的侧表面上留下氮化硅间隔物。 两步法包括使用Cl2 / He化学法首先蚀刻掉70％的氮化硅层，并且使用SF6 / CHF3 / He化学法在半导体器件结构的顶表面上第二次蚀刻剩余的氮化硅。

公开(公告)号：US6063711A

公开(公告)日：2000-05-16

申请号：US69456

申请日：1998-04-28

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Chu-Yun Fu ,  Jhon-Jhy Liaw

IPC分类号： H01L21/768 ,  H01L21/304 ,  B24B1/00 ,  H01L21/461

CPC分类号： H01L21/7681 ,  H01L21/76807

摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.

摘要翻译： 公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。 由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。 因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

公开(公告)号：US08377733B2

公开(公告)日：2013-02-19

申请号：US12890913

申请日：2010-09-27

申请人： Chih-Hui Huang ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu

发明人： Chih-Hui Huang ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC分类号： H01L21/00

CPC分类号： H01L27/1464 ,  H01L27/14625 ,  H01L27/14685

摘要： The present disclosure provides an image sensor device that exhibits improved quantum efficiency. For example, a backside illuminated (BSI) image sensor device is provided that includes a substrate having a front surface and a back surface; a light sensing region disposed at the front surface of the substrate; and an antireflective layer disposed over the back surface of the substrate. The antireflective layer has an index of refraction greater than or equal to about 2.2 and an extinction coefficient less than or equal to about 0.05 when measured at a wavelength less than 700 nm.

摘要翻译： 本公开提供了一种显示出提高的量子效率的图像传感器装置。 例如，提供了背面照明（BSI）图像传感器装置，其包括具有前表面和后表面的基板; 设置在所述基板的前表面的感光区域; 以及设置在基板的背面上的抗反射层。 当在小于700nm的波长下测量时，抗反射层的折射率大于或等于约2.2，消光系数小于或等于约0.05。