公开(公告)号：US20170103965A1

公开(公告)日：2017-04-13

申请号：US15277366

申请日：2016-09-27

Applicant: KILSOO KIM

Inventor： KILSOO KIM

IPC: H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A data storage device may include a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.

公开(公告)号：US20150155266A1

公开(公告)日：2015-06-04

申请号：US14613357

申请日：2015-02-03

Applicant: KILSOO KIM ,  SunWon KANG

Inventor： KILSOO KIM ,  SunWon KANG

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.

Abstract translation: 提供一种半导体封装，其包括具有位于其中心区域中的开口的封装基板和邻近开口设置的电路图案。 第一半导体芯片位于封装衬底上并且包括第一焊盘。 一对第二半导体芯片在开口之间彼此间隔开，并且安装在封装衬底和第一半导体芯片之间。 每个第二半导体芯片包括第二接合焊盘。 还提供连接元件以将第二接合焊盘电连接到第一接合焊盘中相应的一个。

公开(公告)号：US20140175673A1

公开(公告)日：2014-06-26

申请号：US14064110

申请日：2013-10-25

Applicant: KILSOO KIM ,  SunWon KANG

Inventor： KILSOO KIM ,  SunWon KANG

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.

Abstract translation: 提供一种半导体封装，其包括具有位于其中心区域中的开口的封装基板和邻近开口设置的电路图案。 第一半导体芯片位于封装衬底上并且包括第一焊盘。 一对第二半导体芯片在开口之间彼此间隔开，并且安装在封装衬底和第一半导体芯片之间。 每个第二半导体芯片包括第二接合焊盘。 还提供连接元件以将第二接合焊盘电连接到第一接合焊盘中相应的一个。