公开(公告)号：US20230209829A1

公开(公告)日：2023-06-29

申请号：US18176656

申请日：2023-03-01

Applicant: KIOXIA CORPORATION

Inventor： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC: H10B43/27 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20240306393A1

公开(公告)日：2024-09-12

申请号：US18666035

申请日：2024-05-16

Applicant: Kioxia Corporation

Inventor： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC: H10B43/27 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20220216232A1

公开(公告)日：2022-07-07

申请号：US17700951

申请日：2022-03-22

Applicant: KIOXIA CORPORATION

Inventor： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11551 ,  H01L29/792 ,  H01L27/11563 ,  H01L27/11556

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.