公开(公告)号：US20230209829A1

公开(公告)日：2023-06-29

申请号：US18176656

申请日：2023-03-01

申请人： KIOXIA CORPORATION

发明人： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC分类号： H10B43/27 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20240306393A1

公开(公告)日：2024-09-12

申请号：US18666035

申请日：2024-05-16

申请人： Kioxia Corporation

发明人： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC分类号： H10B43/27 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20220216232A1

公开(公告)日：2022-07-07

申请号：US17700951

申请日：2022-03-22

申请人： KIOXIA CORPORATION

发明人： Toshifumi MINAMI ,  Atsuhiro SATO ,  Keisuke YONEHAMA ,  Yasuyuki BABA ,  Hiroshi SHINOHARA ,  Hideyuki KAMATA ,  Teppei HIGASHITSUJI

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11551 ,  H01L29/792 ,  H01L27/11563 ,  H01L27/11556

摘要： A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

公开(公告)号：US20230317173A1

公开(公告)日：2023-10-05

申请号：US18326587

申请日：2023-05-31

申请人： Kioxia Corporation

发明人： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA ,  Kenichi ABE ,  Hiroshi NAKAMURA ,  Keisuke YONEHAMA ,  Atsuhiro SATO ,  Hiroshi SHINOHARA ,  Yasuyuki BABA ,  Toshifumi MINAMI

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C11/5635 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/3445

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US20220148657A1

公开(公告)日：2022-05-12

申请号：US17585370

申请日：2022-01-26

申请人： KIOXIA CORPORATION

发明人： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA ,  Kenichi ABE ,  Hiroshi NAKAMURA ,  Keisuke YONEHAMA ,  Atsuhiro SATO ,  Hiroshi SHINOHARA ,  Yasuyuki BABA ,  Toshifumi MINAMI

IPC分类号： G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.