公开(公告)号：US11270981B2

公开(公告)日：2022-03-08

申请号：US17023617

申请日：2020-09-17

Applicant: KIOXIA CORPORATION

Inventor： Mikihiko Ito ,  Masaru Koyanagi ,  Masafumi Nakatani ,  Shinya Okuno ,  Shigeki Nagasaka ,  Masahiro Yoshihara ,  Akira Umezawa ,  Satoshi Tsukiyama ,  Kazushige Kawasaki

IPC: G11C16/30 ,  H01L25/065 ,  G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  G11C16/26 ,  H01L27/10 ,  G11C16/08 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

公开(公告)号：US11871576B2

公开(公告)日：2024-01-09

申请号：US17113285

申请日：2020-12-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Mie Matsuo ,  Kenichiro Yoshii ,  Koichiro Shindo ,  Kazushige Kawasaki ,  Tomoya Sanuki

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US11568901B2

公开(公告)日：2023-01-31

申请号：US17470955

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Kazushige Kawasaki ,  Masayuki Miura ,  Hideko Mukaida

IPC: G11C5/06 ,  H01L23/10

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0≤t1

公开(公告)号：US20230282536A1

公开(公告)日：2023-09-07

申请号：US17897077

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazushige Kawasaki ,  Satoru Itakura

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/552 ,  H01L24/48 ,  H01L25/0657 ,  H01L21/568 ,  H01L24/05 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: According to one embodiment, a semiconductor device includes a wiring substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. A first electrode is on the first surface. A semiconductor element is on the wiring substrate and electrically connected to the first electrode. A resin layer covers the semiconductor element and the first surface from a first direction orthogonal to the first surface. A portion of the resin layer contacts the side surface of the wiring substrate from a second direction parallel to the first surface. The resin layer has an outside side surface that is substantially parallel to the first direction.