公开(公告)号：US20230317179A1

公开(公告)日：2023-10-05

申请号：US17899014

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Mitsuhiro ABE ,  Yasuhiro HIRASHIMA ,  Mitsuaki HONMA

IPC: G11C16/32 ,  H01L25/065

CPC classification number: G11C16/32 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

公开(公告)号：US20240274219A1

公开(公告)日：2024-08-15

申请号：US18447108

申请日：2023-08-09

Applicant: Kioxia Corporation

Inventor： Mitsuaki HONMA

IPC: G11C29/52 ,  G11C7/10

CPC classification number: G11C29/52 ,  G11C7/1066 ,  G11C7/1069

Abstract: A memory system includes a plurality of memory cells each storing a first bit and a second bit and a control circuit. The control circuit is reads out first data, first partial data, and second partial data, each corresponding to the first bit, from the plurality of memory cells, read out second data, third partial data, and fourth partial data, each corresponding to the second bit, from the plurality of memory cells, generate first compressed data based on an OR operation of the first partial data and the third partial data, generate second compressed data based on an OR operation of the second partial data and the fourth partial data, and transmit the first data, the second data, the first compressed data, and the second compressed data to an external memory controller.

公开(公告)号：US20250095767A1

公开(公告)日：2025-03-20

申请号：US18970707

申请日：2024-12-05

Applicant: Kioxia Corporation

Inventor： Mitsuaki HONMA

IPC: G11C29/52 ,  G11C7/10

Abstract: A nonvolatile memory includes a memory cell transistor storing information of a plurality of bits including first through third bits, a word line, a sense amplifier unit, and a control circuit which controls the word line and the sense amplifier unit. The control circuit includes first through third latch circuits, and performs plural read operations including a first read operation to read out the first bit into the first latch circuit and generate data in the second and third latch circuits, a second read operation performed after the first read operation to read out the second bit into the first latch circuit and update the data in the second and third latch circuits, and a third read operation performed after the second read operation to read out the third bit into the first latch circuit and update the data in the second and third latch circuits.

公开(公告)号：US20240311294A1

公开(公告)日：2024-09-19

申请号：US18673842

申请日：2024-05-24

Applicant: Kioxia Corporation

Inventor： Keisuke AZUMA ,  Mitsuaki HONMA ,  Daisuke ARIZONO

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: According to an embodiment, a memory system includes a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller configured to control the non-volatile memory. The non-volatile memory is configured to output first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit to the memory controller. The memory controller is configured to execute error correction processing using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.

公开(公告)号：US20230207000A1

公开(公告)日：2023-06-29

申请号：US17885382

申请日：2022-08-10

Applicant: Kioxia Corporation

Inventor： Mitsuaki HONMA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/26

Abstract: According to one embodiment, a memory device is configured to execute an efficient read operation is provided. The memory device includes a plurality of memory cells, a word line, and a controller. Each of the memory cells stores first to fifth bit data based on the threshold voltage. The memory cells store a first page to a fifth page respectively corresponding to the first bit data to the fifth bit data. A word line is coupled to the memory cells. A controller executes a read operation for reading data from the memory cells by applying a read voltage to the word line. Numbers of times the controller applies read voltages different from one another to the word line in read operations for the first page to the fifth page are 7, 6, 6, 6, and 6, respectively.

公开(公告)号：US20230170004A1

公开(公告)日：2023-06-01

申请号：US17931945

申请日：2022-09-14

Applicant: Kioxia Corporation

Inventor： Keisuke AZUMA ,  Mitsuaki HONMA ,  Daisuke ARIZONO

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1069 ,  G11C7/06 ,  G11C7/12

Abstract: According to an embodiment, a memory system comprising: a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit and a second bit, and configured to calculate third soft bit data based on a logical sum calculation using at least first soft bit data corresponding to the first bit and second soft bit data corresponding to the second bit; and a memory controller configured to restore the first soft bit data and the second soft bit data based on at least first hard bit data corresponding to the first bit, second hard bit data corresponding to the second bit, and the third soft bit data.