公开(公告)号：US11430525B2

公开(公告)日：2022-08-30

申请号：US17064952

申请日：2020-10-07

Applicant: KIOXIA CORPORATION

Inventor： Tomoko Araya ,  Mitsuaki Honma

IPC: G11C16/26 ,  G11C16/04 ,  G11C29/52 ,  G11C11/56 ,  G11C11/02 ,  G11C11/06 ,  G06F11/10 ,  G11C16/02 ,  G11C16/06

Abstract: According to one embodiment, a memory device, includes a first memory cell, and a second memory cell adjacent to the first memory cell; and a sequencer configured to, when data is read from the first memory cell: perform a first read operation on the second memory cell; perform a second read operation on the first memory cell; perform a third read operation on the first memory cell by applying a voltage different from that applied in the second read operation to a gate of the second memory cell; and generate first data stored in the first memory cell and second data for correcting the first data, based on results of the first to third read operations.

公开(公告)号：US11915778B2

公开(公告)日：2024-02-27

申请号：US17654890

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Daisuke Arizono ,  Akio Sugahara ,  Mitsuhiro Abe ,  Mitsuaki Honma

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1039 ,  G11C7/1087

Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.

公开(公告)号：US12198779B2

公开(公告)日：2025-01-14

申请号：US18447108

申请日：2023-08-09

Applicant: Kioxia Corporation

Inventor： Mitsuaki Honma

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/52

Abstract: A memory system includes a plurality of memory cells each storing a first bit and a second bit and a control circuit. The control circuit is reads out first data, first partial data, and second partial data, each corresponding to the first bit, from the plurality of memory cells, read out second data, third partial data, and fourth partial data, each corresponding to the second bit, from the plurality of memory cells, generate first compressed data based on an OR operation of the first partial data and the third partial data, generate second compressed data based on an OR operation of the second partial data and the fourth partial data, and transmit the first data, the second data, the first compressed data, and the second compressed data to an external memory controller.

公开(公告)号：US12183405B2

公开(公告)日：2024-12-31

申请号：US17899014

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Mitsuhiro Abe ,  Yasuhiro Hirashima ,  Mitsuaki Honma

IPC: G11C16/32 ,  H01L25/065

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.