公开(公告)号：US12087396B2

公开(公告)日：2024-09-10

申请号：US17898981

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Takehisa Kurosawa ,  Akio Sugahara ,  Mitsuhiro Abe ,  Hisashi Fujikawa ,  Yuji Nagai ,  Zhao Lu

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/20

Abstract: A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

公开(公告)号：US12020772B2

公开(公告)日：2024-06-25

申请号：US17716295

申请日：2022-04-08

Applicant: Kioxia Corporation

Inventor： Yasuhiro Hirashima ,  Mitsuhiro Abe ,  Norichika Asaoka

IPC: G11C7/10 ,  G11C29/12

CPC classification number: G11C7/1093 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C29/1201

Abstract: A semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first circuit configured to output a fourth signal based on a signal selected and output by the first select circuit; a first output buffer configured to output a fifth signal based on the signal selected and output by the first select circuit; a first output pad configured to externally output the fifth signal; and a counter configured to count a number of times the fourth signal is output.

公开(公告)号：US11915778B2

公开(公告)日：2024-02-27

申请号：US17654890

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Daisuke Arizono ,  Akio Sugahara ,  Mitsuhiro Abe ,  Mitsuaki Honma

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1039 ,  G11C7/1087

Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.

公开(公告)号：US12183405B2

公开(公告)日：2024-12-31

申请号：US17899014

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Mitsuhiro Abe ,  Yasuhiro Hirashima ,  Mitsuaki Honma

IPC: G11C16/32 ,  H01L25/065

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

公开(公告)号：US12136469B2

公开(公告)日：2024-11-05

申请号：US17896907

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Shintaro Hayashi ,  Mitsuhiro Abe ,  Naoaki Kanagawa

IPC: G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C16/04 ,  G11C16/26

Abstract: A semiconductor memory device includes a memory cell array, a storing unit that stores data read out from the memory cell array in storage circuits, an output circuit, and a control circuit. In response to a read request, the control circuit adjusts the value of a read pointer of the storing unit, controls the storing unit to sequentially output to the output circuit first and second data stored in first and second storage circuits of the storing unit, respectively, the read pointer having a first value that references the first storage circuit when the first data is output, and a second value that references the second storage circuit when the second data is output, and controls the output circuit to transmit the first and second data to the memory controller as dummy data, and thereafter to transmit at least third data to the memory controller as read data.