公开(公告)号：US20210264990A1

公开(公告)日：2021-08-26

申请号：US17244246

申请日：2021-04-29

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C16/08 ,  H01L27/115

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US20240296895A1

公开(公告)日：2024-09-05

申请号：US18662238

申请日：2024-05-13

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  H10B69/00

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459 ,  H10B69/00

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US20210398598A1

公开(公告)日：2021-12-23

申请号：US17348814

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Taira SHIBUYA ,  Noboru SHIBATA ,  Hironori UCHIKAWA

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/12 ,  G11C16/08 ,  G11C7/06

Abstract: A semiconductor memory device according to an embodiment includes first memory cells, second memory cells, and a controller. A threshold voltage of each of the first memory cells and the second memory cells is included in one of first through sixteenth state. 8-bit data that includes a first through eighth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell. The controller is configured to: apply in parallel a plurality of types of read voltages to each of the first memory cells and the second memory cells and externally output data confirmed based on first data read from the first memory cells and second data read from the second memory cells.

公开(公告)号：US20230253054A1

公开(公告)日：2023-08-10

申请号：US18134719

申请日：2023-04-14

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/32 ,  H10B69/00

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US20200211655A1

公开(公告)日：2020-07-02

申请号：US16724100

申请日：2019-12-20

Applicant: KIOXIA CORPORATION

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G06F3/06

Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.