公开(公告)号：US11838152B2

公开(公告)日：2023-12-05

申请号：US17682872

申请日：2022-02-28

Applicant: Kioxia Corporation

Inventor： Takashi Toi

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H01L23/522 ,  H03M1/12 ,  H03F3/189

CPC classification number: H04L25/03057 ,  H01L23/5227 ,  H03F3/189 ,  H03M1/12 ,  H04L25/03878

Abstract: A semiconductor integrated circuit includes a substrate including a first wiring layer and a second wiring layer that is separated from the first wiring layer in a stacking direction, and an equalization circuit formed on the substrate to amplify a signal level of a part of a frequency bandwidth included in a differential input signal including a first signal and a second signal, and output a differential output signal including a third signal and a fourth signal, in which the equalization circuit includes a first transistor, a first inductor element, a second transistor, and a second inductor element, each of the first inductor element and the second inductor element has a first inductor portion, a second inductor portion, and a third inductor portion, the first inductor portion and the second inductor portion include single-layer winding coils, a third end portion of the third inductor portion is electrically connected to a first end portion of the first inductor portion, and a fourth end portion of the third inductor portion is electrically connected to a second end portion of the second inductor portion.

公开(公告)号：US11223378B2

公开(公告)日：2022-01-11

申请号：US17010207

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Takashi Toi

IPC: H04B1/04 ,  H04L25/08 ,  H04L25/03

Abstract: A semiconductor integrated circuit includes a first circuit configured to carry out digital-to-analog conversion on input data; a high-pass filter configured to reduce a component, the component having a frequency lower than a predetermined cutoff frequency, in delayed input data obtained by delaying the input data, and output the delayed input data; a second circuit configured to carryout the digital-to-analog conversion on the delayed input data that passes through the high-pass filter; and a third circuit configured to drive a transmission signal, the transmission signal based on an addition signal obtained by adding an output signal of the first circuit and an output signal of the second circuit.

公开(公告)号：US20240429266A1

公开(公告)日：2024-12-26

申请号：US18743825

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Takashi Toi

IPC: H10B41/00

Abstract: According to one embodiment, a semiconductor circuit includes a semiconductor substrate, a first T-coil including a first inductive element and a second inductive element which are coupled in series, and a second T-coil including a third inductive element and a fourth inductive element which are coupled in series. A part of the first T-coil is provided at a first position. A part of the second T-coil is provided at a second position to overlap with the part of the first T-coil in the vertical direction. A first distance from the semiconductor substrate to the first position is different from a second distance from the semiconductor substrate to the second position. The first T-coil is configured to receive a first signal having a first polarity of a differential signal. The second T-coil is configured to receive a second signal having a second polarity different from the first polarity.

公开(公告)号：US11334286B2

公开(公告)日：2022-05-17

申请号：US17098757

申请日：2020-11-16

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Kobayashi ,  Jun Deguchi ,  Junji Wadatsumi ,  Takashi Toi

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  H04L7/00 ,  H04L7/033

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.