公开(公告)号：US12164981B2

公开(公告)日：2024-12-10

申请号：US17198448

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Radu Berdan ,  Daisuke Miyashita ,  Jun Deguchi

IPC: G06G7/16 ,  G06F7/544

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

公开(公告)号：US11734298B2

公开(公告)日：2023-08-22

申请号：US17304190

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Yasuto Hoshi ,  Daisuke Miyashita ,  Jun Deguchi

IPC: G06F16/25 ,  G06F16/242 ,  G06F16/245 ,  G06N3/04 ,  G06N3/045 ,  G06N3/08 ,  G06N3/048

CPC classification number: G06F16/258 ,  G06F16/243 ,  G06F16/245 ,  G06N3/045 ,  G06N3/048 ,  G06N3/08

Abstract: According to one embodiment, an information processing device includes: an encoder including a first layer and a second layer which are coupled in series; and a decoder. The encoder is configured to: generate, based on first data, a first key and a first value in the first layer, and a second key and a second value in the second layer; and generate, based on second data different from the first data, a first query in the first layer, and a second query in the second layer. The decoder is configured to: generate third data which is included in the first data and is not included in the second data, based on the first key, the first value, the first query, the second key, the second value, and the second query.

公开(公告)号：US20220147821A1

公开(公告)日：2022-05-12

申请号：US17344192

申请日：2021-06-10

Applicant: Kioxia Corporation

Inventor： Kengo Nakata ,  Daisuke Miyashita ,  Jun Deguchi

IPC: G06N3/08 ,  G06N3/04

Abstract: According to one embodiment, a processor is configured to calculate a calculation amount in inference time of a neural network, using a result of summing, with respect to a group to which quantization is applied, products of the number of product-sum operations and bit widths of weight for the product-sum operations in the neural network. Then, the processor is configured to optimize a value of the weight and a quantization step size to minimize the recognition error by the neural network based on the calculated calculation amount, and execute computing about the neural network based on the optimized weight and the quantization step size.

公开(公告)号：US12068031B2

公开(公告)日：2024-08-20

申请号：US17901239

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Jun Deguchi ,  Daisuke Miyashita ,  Atsushi Kawasumi ,  Hidehiro Shiga ,  Shinji Miyano ,  Shinichi Sasaki

IPC: G11C16/08 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

公开(公告)号：US11334286B2

公开(公告)日：2022-05-17

申请号：US17098757

申请日：2020-11-16

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Kobayashi ,  Jun Deguchi ,  Junji Wadatsumi ,  Takashi Toi

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  H04L7/00 ,  H04L7/033

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.