公开(公告)号：US20230207012A1

公开(公告)日：2023-06-29

申请号：US18171540

申请日：2023-02-20

Applicant: KIOXIA CORPORATION

Inventor： Takatoshi MINAMOTO ,  Toshiki HISADA ,  Dai NAKAMURA

IPC: G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528

Abstract: A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

公开(公告)号：US20220223611A1

公开(公告)日：2022-07-14

申请号：US17369453

申请日：2021-07-07

Applicant: Kioxia Corporation

Inventor： Takatoshi MINAMOTO ,  Sho TOKAIRIN ,  Yoshinao SUZUKI

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

Abstract: A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source.

公开(公告)号：US20250095760A1

公开(公告)日：2025-03-20

申请号：US18823749

申请日：2024-09-04

Applicant: Kioxia Corporation

Inventor： Takatoshi MINAMOTO

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: According to embodiments, a semiconductor memory device includes a memory string including a first select transistor, a first memory cell, and a second memory cell, a bit line, a first word line, a second word line, and a control circuit configured to execute a write operation including a program operation and a program verify operation. The control circuit is configured to raise a voltage of the second word line to a first voltage based on a first condition, in a case of executing the program verify operation of the first memory cell, and to raise a voltage of the first word line to the first voltage based on a second condition different from the first condition, in a case of executing the program verify operation of the second memory cell.