公开(公告)号：US20220189563A1

公开(公告)日：2022-06-16

申请号：US17689300

申请日：2022-03-08

Applicant: KIOXIA CORPORATION

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US20240371448A1

公开(公告)日：2024-11-07

申请号：US18775119

申请日：2024-07-17

Applicant: KIOXIA CORPORATION

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G06F5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US20230326535A1

公开(公告)日：2023-10-12

申请号：US18333661

申请日：2023-06-13

Applicant: KIOXIA CORPORATION

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

CPC classification number: G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/10 ,  G06F5/06 ,  G06F13/1673 ,  G11C16/0483

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US20240429921A1

公开(公告)日：2024-12-26

申请号：US18743540

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Yasuhiro HIRASHIMA ,  Toshiyuki KOUCHI ,  Junya MATSUNO ,  Masato DOME

IPC: H03K21/38 ,  G06F1/12 ,  H03K21/40

Abstract: A semiconductor device including an oscillator configured to output a first signal, and circuitry configured to count a cycle number of the first signal OSC. Before the oscillator outputs an N-th (N is an integer equal to or larger than 2) cycle of the first signal, the circuitry changes a count value of the cycle number of the first signal to N.

公开(公告)号：US20230352093A1

公开(公告)日：2023-11-02

申请号：US18177779

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Yasuhiro HIRASHIMA ,  Toshiyuki KOUCHI

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/32

Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.