公开(公告)号：US20230297239A1

公开(公告)日：2023-09-21

申请号：US17898370

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Kenta SHIBASAKI ,  Yoshihiko SHINDO ,  Yasuhiro HIRASHIMA ,  Akio SUGAHARA ,  Shigeki NAGASAKA ,  Dai NAKAMURA ,  Yousuke HAGIWARA

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0653

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

公开(公告)号：US20220189563A1

公开(公告)日：2022-06-16

申请号：US17689300

申请日：2022-03-08

Applicant: KIOXIA CORPORATION

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US20240371448A1

公开(公告)日：2024-11-07

申请号：US18775119

申请日：2024-07-17

Applicant: KIOXIA CORPORATION

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G06F5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US20230326535A1

公开(公告)日：2023-10-12

申请号：US18333661

申请日：2023-06-13

Applicant: KIOXIA CORPORATION

Inventor： Shinya OKUNO ,  Shigeki NAGASAKA ,  Toshiyuki KOUCHI

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/16

CPC classification number: G11C16/32 ,  G11C16/26 ,  G11C16/16 ,  G11C16/12 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/10 ,  G06F5/06 ,  G06F13/1673 ,  G11C16/0483

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.