公开(公告)号：US20220392673A1

公开(公告)日：2022-12-08

申请号：US17769855

申请日：2020-09-24

Applicant: KOA CORPORATION

Inventor： Yasushi AKAHANE ,  Nobuhiko TAMADA

IPC: H01C1/14

Abstract: A chip component comprises: an insulating substrate on which a resistor serving as a functional element is formed; a pair of internal electrodes (front electrodes, end surface electrodes, and back electrodes) that is formed to cover both end portions of the insulating substrate and connected to the resistor; a barrier layer that is formed on a surface of each of the internal electrodes and mainly composed of nickel; and an external connection layer that is formed on a surface of the barrier layer and mainly composed of tin, and the barrier layer is composed of alloy plating (Ni—P) including nickel and phosphorus, which is formed by electrolytic plating, and a content ratio of phosphorus relative to nickel is set in a range of 0.5% to 5% so that the barrier layer has magnetism.

公开(公告)号：US20240096926A1

公开(公告)日：2024-03-21

申请号：US18276215

申请日：2022-02-24

Applicant: KOA CORPORATION

Inventor： Yasushi AKAHANE

IPC: H01C1/142 ,  H01C7/00 ,  H01L23/13

CPC classification number: H01L28/20 ,  H01C1/142 ,  H01C7/003 ,  H01L23/13

Abstract: Provided is a mounting structure for a chip component having high thermal shock resistance. In amounting structure for a chip resistor 1 according to the present invention, a separation distance L1 between a pair of back surface electrodes 3 formed on an insulating substrate 2 of a chip resistor 20 is set to be shorter than a separation distance L2 between a pair of lands 31 provided on a circuit board 30. Each of the back surface electrodes 3 is formed with a thick portion (first electrode portion 3a), and an external electrode 9 deposited on the back surface electrode 3 is connected on the corresponding land 31 via solder 32 with a top portion of the thick portion made positioned directly above an inner end of the land 31.

公开(公告)号：US20240049399A1

公开(公告)日：2024-02-08

申请号：US18266722

申请日：2021-12-02

Applicant: KOA CORPORATION

Inventor： Yasushi AKAHANE

IPC: H05K3/34 ,  H01C7/00 ,  H01C1/142 ,  H01C17/28 ,  H01C17/00

CPC classification number: H05K3/3431 ,  H01C7/003 ,  H01C1/142 ,  H01C17/283 ,  H01C17/006

Abstract: A chip resistor according to the present invention includes an insulating substrate, a pair of back surface electrodes, a pair of top surface electrodes, a resistor, and a pair of end face electrodes. The back surface electrode includes the first electrode portion located inwardly and away from the end face of the insulating substrate, and the two second electrode portions arranged on two portions, respectively, in the short direction of the insulating substrate with the cutout portion, which is positioned between the end face of the insulating substrate and the first electrode portion, being interposed therebetween, and the maximum height of the first electrode portion is set to be more than the maximum height of the second electrode portions.

公开(公告)号：US20230144364A1

公开(公告)日：2023-05-11

申请号：US17911824

申请日：2021-02-26

Applicant: KOA CORPORATION

Inventor： Yasushi AKAHANE ,  Nobuhiko TAMADA

IPC: H01L23/498

CPC classification number: H01L23/49883 ,  H01L23/49822

Abstract: A chip resistor comprises an insulating substrate (component body) on which a resistor is formed, a connection terminal (front electrodes, end face electrodes, and back electrodes) formed at both end portions of the insulating substrate, an under layer formed by electrolytic plating to cover the connection terminal, a barrier layer formed by electrolytic plating to cover the under layer, and an external connection layer which is mainly composed of tin and formed on a surface of the barrier layer, wherein the barrier layer is made of alloy plating mainly composed of nickel and containing 3% to 15% of phosphorus, and the under layer is formed of a copper plated layer that is at least either more malleable or more ductile than the barrier layer.

公开(公告)号：US20240153678A1

公开(公告)日：2024-05-09

申请号：US17769311

申请日：2020-09-24

Applicant: KOA CORPORATION

Inventor： Yasushi AKAHANE ,  Nobuhiko TAMADA

IPC: H01C17/00 ,  C25D3/56 ,  C25D5/12 ,  C25D7/06 ,  C25D21/12 ,  H01C1/032 ,  H01C1/142 ,  H01C17/242

CPC classification number: H01C17/006 ,  C25D3/562 ,  C25D5/12 ,  C25D7/0642 ,  C25D21/12 ,  H01C1/032 ,  H01C1/142 ,  H01C17/242

Abstract: A chip component 10 comprises: an insulating substrate 1 on which a resistor 3 serving as a functional element is formed; a pair of internal electrodes (front electrodes 2, end surface electrodes 6, and back electrodes 5) that is formed to cover both end portions of the insulating substrate 1 and connected to the resistor 3; a barrier layer 8 that is formed on a surface of each of the internal electrodes and mainly composed of nickel; and an external connection layer 9 that is formed on a surface of the barrier layer 8 and mainly composed of tin, and the barrier layer 8 is composed of alloy plating (Ni—P) including nickel and phosphorus, which is formed by electrolytic plating, and a content rate of phosphorus in the alloy plating of an inner region is made different from that of an outer region so that at least the inner region of the barrier layer 8 has magnetic properties.

公开(公告)号：US20180158578A1

公开(公告)日：2018-06-07

申请号：US15572847

申请日：2016-04-11

Applicant: KOA Corporation

Inventor： Yasushi AKAHANE ,  Shinsuke CHIHARA

IPC: H01C1/148 ,  H01C1/142

CPC classification number: H01C1/148 ,  H01C1/028 ,  H01C1/14 ,  H01C1/142 ,  H01C7/00 ,  H01C7/003 ,  H01C17/02

Abstract: Provided is a chip resistor in which cracks, fracture, etc. can be surely prevented from occurring due to thermal stress in solder bonding portions. The chip resistor 1 includes: a ceramic substrate 2 that is shaped like a cuboid; a pair of front electrodes 3 that are provided on lengthwise opposite end portions of a front surface of the ceramic substrate 2; a resistor body 4 that is provided between and connected to the two front electrodes 3; a protective layer 5 that covers the resistor body 4; a pair of back electrodes 6 that are provided on lengthwise opposite end portions of a back surface of the ceramic substrate 2; end-surface electrodes 7 through which the front electrodes 3 and the back electrodes 6 are electrically conductively connected to each other respectively; external electrodes 8 that cover the end-surface electrodes 7; and a pair of insulating resin layers 9 that are provided to cover edge portions of the back electrodes 6; wherein: the pair of insulating resin layers 9 are opposed to each other with interposition of a predetermined interval therebetween on the back surface of the ceramic substrate 2; and at least opposed side end portions of the insulating resin layers 9 are exposed from the external electrodes 8.