公开(公告)号：US20220399353A1

公开(公告)日：2022-12-15

申请号：US17538747

申请日：2021-11-30

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young KWAK ,  Eunpyo PARK ,  Suyoun LEE ,  Inho KIM ,  Jong-Keuk PARK ,  Jaewook KIM ,  Jongkil PARK ,  YeonJoo JEONG

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L29/43 ,  H01L29/66

Abstract: A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.

公开(公告)号：US20220156565A1

公开(公告)日：2022-05-19

申请号：US17205790

申请日：2021-03-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young KWAK ,  Suyoun LEE ,  Inho KIM ,  Jong-Keuk PARK ,  Kyeong Seok LEE ,  Jaewook KIM ,  Jongkil PARK ,  YeonJoo JEONG ,  Gyuweon HWANG

IPC: G06N3/063 ,  G11C16/04 ,  G11C16/10

Abstract: Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.

公开(公告)号：US20240172436A1

公开(公告)日：2024-05-23

申请号：US17990333

申请日：2022-11-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young KWAK ,  Minkyung KIM ,  Suyoun LEE ,  Inho KIM ,  Jong-Keuk PARK ,  Jaewook KIM ,  Jongkil PARK ,  YeonJoo JEONG

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A flash memory device including multi-layered oxide for neuromorphic computing system is disclosed. According to embodiments, the flash memory device includes: a substrate; a channel layer disposed on the substrate; source/drain patterns disposed on both ends of the channel layer; a tunneling insulating layer disposed on the channel layer; a trapping layer disposed on the tunneling insulating layer and including a plurality of nitride layers; an intermediate barrier layer interposed within the trapping layer, and including an oxide layer, the oxide layer having a high dielectric constant; a blocking insulating layer disposed on the trapping layer; and an upper gate disposed on the blocking insulating layer.

公开(公告)号：US20220138546A1

公开(公告)日：2022-05-05

申请号：US17205620

申请日：2021-03-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young KWAK ,  Suyoun LEE ,  Inho KIM ,  Jong-Keuk PARK ,  Kyeong Seok LEE ,  Jaewook KIM ,  Jongkil PARK ,  YeonJoo JEONG ,  Gyuweon HWANG

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54

Abstract: A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.

公开(公告)号：US20210089893A1

公开(公告)日：2021-03-25

申请号：US16971917

申请日：2019-12-31

Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION ,  KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Ki Young CHOI ,  Jae Hyun KIM ,  Chae Un LEE ,  Joonyeon CHANG ,  Joon Young KWAK ,  Jaewook KIM

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F17/18

Abstract: An embodiment of the present disclosure discloses a method of process variation compensating through activation value adjustment of an analog binarized neural network circuit that may recover a decrease in recognition rate performance up to an almost perfect level, even if a binarized neural network is implemented as an analog circuit such that recognition rate performance is decreased due to process variation.

公开(公告)号：US20230170017A1

公开(公告)日：2023-06-01

申请号：US17966305

申请日：2022-10-14

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jaewook KIM ,  Kyu Sik MUN ,  Yeonjoo JEONG ,  Joon Young KWAK ,  Jongkil PARK ,  Suyoun LEE ,  Jong-Keuk PARK ,  Inho KIM ,  Seongsik PARK

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/0061

Abstract: The present disclosure relates to a nonlinearity compensation circuit for a memristive device. The circuit according to an embodiment includes at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to adjust a pulse width of an update pulse to be applied to the memristive device; and the memristive device to which the modulated update pulse is applied.