Abstract:
An exemplary embodiment relates to a nano-color coating layer and a method of forming the same, and more particularly, to a color structure representing a back side-reflection color with metallic luster and high chroma when observed in a substrate incident mode by greatly enhancing light absorbance at a specific wavelength using a resonance structure in which a light absorbing material is inserted between a transparent substrate and an upper mirror layer. In addition, the exemplary embodiment provides a color structure which controls metallic luster and texture of a high-chroma color from gloss-semi-gloss-matte texture in various ways by introducing a haze surface structure in which light scattering occurs on at least one surface of the transparent substrate.
Abstract:
A method for manufacturing an electrode for hydrogen production using a tungsten carbide nanoflake may include: forming a tungsten carbide nanoflake on a nanocrystalline diamond film by means of a chemical vapor deposition process in which hydrogen plasma is applied; and increasing activity of the tungsten carbide nanoflake to a hydrogen evolution reaction by removing an oxide layer or a graphene layer from a surface of the tungsten carbide nanoflake. Since an oxide layer and/or a graphene layer of a surface of tungsten carbide is removed by means of cyclic cleaning after tungsten carbide is formed, hydrogen evolution reaction (HER) activity of the tungsten carbide may be increased, thereby enhancing utilization as a catalyst electrode.
Abstract:
A plasmonic nano-color coating layer includes a composite layer including a plurality of metal particle layers and a plurality of matrix layers and having a periodic multilayer structure in which the metal particle layers and the matrix layers are alternately arranged, a dielectric buffer layer located below the composite layer, and a mirror layer located below the dielectric buffer layer, wherein the color of the plasmonic nano-color coating layer is determined based on a nominal thickness of the metal particle layer and a separation between the metal particle layers.
Abstract:
The present disclosure relates to a thin-film solar cell capable of independently adjusting transparency and color, which is capable of selectively controlling transmittance while independently adjusting external and internal colors within a range in which degradation of photoelectric conversion efficiency is minimized, and a method of manufacturing the same, and the thin-film solar cell capable of independently adjusting transparency and color according to the present disclosure includes a structure in which a back transparent electrode, a light absorption layer, a front transparent electrode, and a front color layer are sequentially stacked on a transparent substrate, in which a light transmission part region, to which the back transparent electrode is exposed, is formed by removing the front color layer, the front transparent electrode, and the light absorption layer.
Abstract:
A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.
Abstract:
A method for fabricating a nanoantenna array may include forming a resist layer on a substrate, forming a focusing layer having a dielectric microstructure array on the resist layer, diffusing light one-dimensionally in a specific direction by using a linear diffuser, forming an anisotropic pattern on the resist layer by illuminating the light diffused by the linear diffuser on the focusing layer and the resist layer, depositing a material suitable for a plasmonic resonance onto the substrate and the resist layer on which the pattern is formed, and forming a nanoantenna array on the substrate by removing the resist layer and the material deposited on the resist layer. A light diffusing angle by the linear diffuser and a size of the dielectric microstructure are determined based on an aspect ratio of the pattern to be formed.
Abstract:
A localized surface plasmon resonance sensor may include a localized surface plasmon excitation layer including a chalcogenide material. The chalcogenide material may include: a first material including at least one of selenium (Se) and tellurium (Te); and a second material including at least one of germanium (Ge) and antimony (Sb). The localized surface plasmon excitation layer may be prepared by forming a thin film including the chalcogenide material and crystallizing the thin film to have a predetermined pattern by irradiating laser on the thin film.
Abstract:
Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.