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公开(公告)号：US20220230059A1
公开(公告)日：2022-07-21
申请号：US17579400
申请日：2022-01-19
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Jong Kil PARK , In Ho KIM , Su Youn LEE , Jong Keuk PARK , Joon Young KWAK , Jae Wook KIM , Yeon Joo JEONG
Abstract: Provided is a method of operating a neuron in a neuromorphic system. The method includes evaluating a membrane potential value at a corresponding time when receiving an input spike, time-modulating a synaptic weight of the membrane potential value and converting the time-modulated synaptic weight into a membrane potential value at a reference time, and generating an output spike when the membrane potential value at the reference time exceeds a certain threshold value. The membrane potential value at the reference time is represented by a floating point number including a predetermined bit of exponent and mantissa, and the floating point number includes time information. The method further includes accessing a memory and scanning a neural state variable when a timer is updated to “0” to update the neural state variable to an updated value at a reference time.
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公开(公告)号：US20230174100A1
公开(公告)日：2023-06-08
申请号：US18073146
申请日：2022-12-01
Applicant: Korea Institute of Science and Technology
Inventor： Jae Wook KIM , Dong Hyuk SHIN , Hyeong Cheol JO , Yeon Joo JEONG , Su Youn LEE , Joon Young KWAK , Jong Kil PARK , In Ho KIM , Jong Keuk PARK , Seong Sik PARK
CPC classification number: B60W60/001 , B60W40/08 , B60W50/04
Abstract: Provided are an autonomous driving system and a correction learning method for autonomous driving. The autonomous driving system includes a sensor configured to collect and output data required for autonomous driving, a first processor configured to output autonomous driving data on the basis of data input from the sensor, a second processor configured to output a driving data adjustment value on the basis of differences between the data input from the sensor, the autonomous driving data input from the first processor, and driving data input from driving by a human driver, and a driving part configured to perform driving on the basis of the autonomous driving data output from the first processor and the driving data adjustment value output from the second processor.
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公开(公告)号：US20230170017A1
公开(公告)日：2023-06-01
申请号：US17966305
申请日：2022-10-14
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Jaewook KIM , Kyu Sik MUN , Yeonjoo JEONG , Joon Young KWAK , Jongkil PARK , Suyoun LEE , Jong-Keuk PARK , Inho KIM , Seongsik PARK
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C13/0061
Abstract: The present disclosure relates to a nonlinearity compensation circuit for a memristive device. The circuit according to an embodiment includes at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to adjust a pulse width of an update pulse to be applied to the memristive device; and the memristive device to which the modulated update pulse is applied.
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公开(公告)号：US20220138546A1
公开(公告)日：2022-05-05
申请号：US17205620
申请日：2021-03-18
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Joon Young KWAK , Suyoun LEE , Inho KIM , Jong-Keuk PARK , Kyeong Seok LEE , Jaewook KIM , Jongkil PARK , YeonJoo JEONG , Gyuweon HWANG
Abstract: A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.
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公开(公告)号：US20210089893A1
公开(公告)日：2021-03-25
申请号：US16971917
申请日：2019-12-31
Inventor： Ki Young CHOI , Jae Hyun KIM , Chae Un LEE , Joonyeon CHANG , Joon Young KWAK , Jaewook KIM
Abstract: An embodiment of the present disclosure discloses a method of process variation compensating through activation value adjustment of an analog binarized neural network circuit that may recover a decrease in recognition rate performance up to an almost perfect level, even if a binarized neural network is implemented as an analog circuit such that recognition rate performance is decreased due to process variation.
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Patent Agency Ranking
公开(公告)号：US20240172436A1
公开(公告)日：2024-05-23
申请号：US17990333
申请日：2022-11-18
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Joon Young KWAK , Minkyung KIM , Suyoun LEE , Inho KIM , Jong-Keuk PARK , Jaewook KIM , Jongkil PARK , YeonJoo JEONG
IPC: H10B43/27
CPC classification number: H10B43/27
Abstract: A flash memory device including multi-layered oxide for neuromorphic computing system is disclosed. According to embodiments, the flash memory device includes: a substrate; a channel layer disposed on the substrate; source/drain patterns disposed on both ends of the channel layer; a tunneling insulating layer disposed on the channel layer; a trapping layer disposed on the tunneling insulating layer and including a plurality of nitride layers; an intermediate barrier layer interposed within the trapping layer, and including an oxide layer, the oxide layer having a high dielectric constant; a blocking insulating layer disposed on the trapping layer; and an upper gate disposed on the blocking insulating layer.
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公开(公告)号：US20230267318A1
公开(公告)日：2023-08-24
申请号：US17872558
申请日：2022-07-25
Applicant: Korea Institute of Science and Technology
Inventor： Joon Young KWAK , Sung Yun PARK , Min Jee KIM , Su Youn LEE
IPC: G06N3/04
CPC classification number: G06N3/049
Abstract: Provided is a neuromorphic system for synaptic learning in a spiking neural network (SNN)-based neuromorphic array structure. Control blocks including a post-synaptic neuron, which generates a post-neuron spike, are disposed on output lines of a synapse array to implement a spike timing dependent plasticity (STDP) operation such that synaptic learning can be stably implemented in an SNN neuromorphic array. Also, a lateral inhibition circuit may be added. When a post-neuron spike is generated by an STDP control block connected to any one output line, the lateral inhibition circuit inhibits STDP control blocks connected to other output lines from generating spikes. Accordingly, learning selectivity can be improved, and thus the performance of an STDP algorithm can be improved.
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公开(公告)号：US20220399353A1
公开(公告)日：2022-12-15
申请号：US17538747
申请日：2021-11-30
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Joon Young KWAK , Eunpyo PARK , Suyoun LEE , Inho KIM , Jong-Keuk PARK , Jaewook KIM , Jongkil PARK , YeonJoo JEONG
IPC: H01L27/11521 , H01L29/788 , H01L29/423 , H01L29/43 , H01L29/66
Abstract: A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.
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公开(公告)号：US20220230060A1
公开(公告)日：2022-07-21
申请号：US17615394
申请日：2019-07-05
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Vladimir KORNIJCUK , Doo Seok JEONG , Joon Young KWAK , Jae Wook KIM , Jong Kil PARK , In Ho KIM , Jong Keuk PARK , Su Youn LEE , Yeon Joo JEONG , Joon Yeon CHANG
Abstract: A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.
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公开(公告)号：US20220156565A1
公开(公告)日：2022-05-19
申请号：US17205790
申请日：2021-03-18
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Joon Young KWAK , Suyoun LEE , Inho KIM , Jong-Keuk PARK , Kyeong Seok LEE , Jaewook KIM , Jongkil PARK , YeonJoo JEONG , Gyuweon HWANG
Abstract: Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.
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