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1.发明申请METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON NITRIDE LAYERS IN A SEMICONDUCTOR DEVICE 有权在半导体器件中用于降低硅氮化物层的方式减少耐药性的方法公开(公告)号：US20080081480A1
公开(公告)日：2008-04-03
申请号：US11742878
申请日：2007-05-01
申请人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
发明人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.
摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。
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2.发明授权Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device 有权用于在半导体器件中的氮化硅层的图案化期间减少抗蚀剂中毒的方法公开(公告)号：US07550396B2
公开(公告)日：2009-06-23
申请号：US11742878
申请日：2007-05-01
申请人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
发明人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
IPC分类号： H01L21/461
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.
摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。
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3.发明授权Dual contact metallization including electroless plating in a semiconductor device 有权双接触金属化，包括在半导体器件中的化学镀公开(公告)号：US08658494B2
公开(公告)日：2014-02-25
申请号：US12854393
申请日：2010-08-11
IPC分类号： H01L21/74
CPC分类号： H01L29/66659 , H01L21/76895 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L29/6659 , H01L29/66628 , H01L29/7835 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.
摘要翻译： 复杂半导体器件的接触元件可以形成用于栅极电极结构和用于分开的工艺序列中的漏极和源极区域，以便施加无电镀技术，而不会导致一种类型的接触开口的不适当的过度填充。 因此，可以实现与降低的总接触电阻相结合的优异的工艺均匀性。 在一些说明性实施例中，钴可以用作接触金属而没有任何额外的导电阻挡材料。
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4.发明申请DUAL CONTACT METALLIZATION INCLUDING ELECTROLESS PLATING IN A SEMICONDUCTOR DEVICE 有权双接触金属化，包括半导体器件中的电镀镀层公开(公告)号：US20110049713A1
公开(公告)日：2011-03-03
申请号：US12854393
申请日：2010-08-11
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L29/66659 , H01L21/76895 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L29/6659 , H01L29/66628 , H01L29/7835 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.
摘要翻译： 复杂半导体器件的接触元件可以形成用于栅极电极结构和用于分开的工艺序列中的漏极和源极区域，以便施加无电镀技术，而不会导致一种类型的接触开口的不适当的过度填充。 因此，可以实现与降低的总接触电阻相结合的优异的工艺均匀性。 在一些说明性实施例中，钴可以用作接触金属而没有任何额外的导电阻挡材料。
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5.发明申请METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS 有权用于防止形成电气短路的方法，通过接触ILD VOIDS公开(公告)号：US20080265365A1
公开(公告)日：2008-10-30
申请号：US11951092
申请日：2007-12-05
申请人： Kai Frohberg , Sven Mueller , Frank Feustel
发明人： Kai Frohberg , Sven Mueller , Frank Feustel
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L21/7682 , H01L21/76837 , H01L29/665 , H01L29/7833
摘要： Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented.
摘要翻译： 场效应晶体管的密集间隔栅极通常导致接触层间电介质中的空隙。 如果这样的空隙由接触通孔打开并填充有导电材料，则可能发生相邻晶体管的相邻接触区域之间的电短路。 通过在两个相邻的接触区域之间形成凹陷，空隙形成在较低的水平。 因此，防止了通过接触通孔打开空隙。
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6.发明授权SOI semiconductor device with reduced topography above a substrate window area 有权SOI衬底窗口区域上方的图形减小的SOI半导体器件公开(公告)号：US08048726B2
公开(公告)日：2011-11-01
申请号：US12914663
申请日：2010-10-28
申请人： Jens Heinrich , Kai Frohberg , Sven Mueller , Kerstin Ruttloff
发明人： Jens Heinrich , Kai Frohberg , Sven Mueller , Kerstin Ruttloff
IPC分类号： H01L21/00 , H01L21/84 , H01L21/302 , H01L21/461
CPC分类号： H01L21/84 , H01L27/1207
摘要： In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.
摘要翻译： 在复杂的SOI器件中，可以在衬底窗口的基础上在晶体衬底材料中形成诸如衬底二极管之类的电路元件，其中可以通过执行附加的平坦化工艺来补偿或至少减少显着的表面形貌，例如 平坦化材料的沉积，以及当形成半导体器件的接触电平时的后续蚀刻工艺。
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7.发明申请METHOD FOR PATTERNING CONTACT ETCH STOP LAYERS BY USING A PLANARIZATION PROCESS 有权使用平面化方法绘制接触蚀刻停止层的方法公开(公告)号：US20080057720A1
公开(公告)日：2008-03-06
申请号：US11692267
申请日：2007-03-28
申请人： Kai Frohberg , Sven Mueller , Christoph Schwan
发明人： Kai Frohberg , Sven Mueller , Christoph Schwan
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76801 , H01L21/823425 , H01L21/823475 , Y10S438/938 , Y10S438/958 , Y10S438/97
摘要： By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.
摘要翻译： 通过执行平坦化工艺，例如基于平坦化层，在形成用于选择性地去除应力接触蚀刻停止层的一部分的抗蚀剂掩模之前，随后沉积的另外的接触蚀刻停止层的应变诱导机构可以是显着的 改进。
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8.发明申请SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE WINDOW AREA 有权SOI半导体器件，具有上面的底层窗口区域公开(公告)号：US20110189825A1
公开(公告)日：2011-08-04
申请号：US12914663
申请日：2010-10-28
申请人： Jens Heinrich , Kai Frohberg , Sven Mueller , Kerstin Ruttloff
发明人： Jens Heinrich , Kai Frohberg , Sven Mueller , Kerstin Ruttloff
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1207
摘要： In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.
摘要翻译： 在复杂的SOI器件中，可以在衬底窗口的基础上在晶体衬底材料中形成诸如衬底二极管之类的电路元件，其中可以通过执行附加的平坦化工艺来补偿或至少减少显着的表面形貌，例如 平坦化材料的沉积，以及当形成半导体器件的接触电平时的后续蚀刻工艺。
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9.发明授权Method for patterning contact etch stop layers by using a planarization process 有权通过使用平坦化工艺图案化接触蚀刻停止层的方法公开(公告)号：US07838354B2
公开(公告)日：2010-11-23
申请号：US11692267
申请日：2007-03-28
申请人： Kai Frohberg , Sven Mueller , Christoph Schwan
发明人： Kai Frohberg , Sven Mueller , Christoph Schwan
IPC分类号： H01L21/8238
CPC分类号： H01L21/31144 , H01L21/76801 , H01L21/823425 , H01L21/823475 , Y10S438/938 , Y10S438/958 , Y10S438/97
摘要： By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.
摘要翻译： 通过执行平坦化工艺，例如基于平坦化层，在形成用于选择性地去除应力接触蚀刻停止层的一部分的抗蚀剂掩模之前，随后沉积的另外的接触蚀刻停止层的应变诱导机构可以是显着的 改进。
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10.发明授权Method for preventing the formation of electrical shorts via contact ILD voids 有权防止通过接触ILD空隙形成电气短路的方法公开(公告)号：US07741191B2
公开(公告)日：2010-06-22
申请号：US11951092
申请日：2007-12-05
申请人： Kai Frohberg , Sven Mueller , Frank Feustel
发明人： Kai Frohberg , Sven Mueller , Frank Feustel
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/76837 , H01L29/665 , H01L29/7833
摘要： Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented.
摘要翻译： 场效应晶体管的密集间隔栅极通常导致接触层间电介质中的空隙。 如果这样的空隙由接触通孔打开并填充有导电材料，则可能发生相邻晶体管的相邻接触区域之间的电短路。 通过在两个相邻的接触区域之间形成凹陷，空隙形成在较低的水平。 因此，防止了通过接触通孔打开空隙。
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