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    Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material
    1.
    发明授权
    Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material 有权
    在包括具有中间缓冲材料的应力层的半导体器件中的层间电介质材料

    公开(公告)号：US08546274B2

    公开(公告)日：2013-10-01

    申请号：US12835967

    申请日：2010-07-14

    申请人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    发明人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

    摘要： A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

    摘要翻译： 可以以保形方式沉积高应力电介质材料，例如拉伸应力材料，以便遵循由高比例尺度的半导体器件的显着表面形貌引起的任何沉积约束，随后沉积具有增强间隙的缓冲材料， 填充能力。 此后，沉积另外的应力诱导层以形成作用于晶体管元件的双重结构，从而提高整体性能，而不增加产生沉积相关不规则性的可能性。 因此，可以提高高标度的半导体器件的生产率以及性能。

    INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS
    3.
    发明申请
    INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS 有权
    包含耐压材料双层结构的半导体器件中的中间层介电材料

    公开(公告)号：US20090166800A1

    公开(公告)日：2009-07-02

    申请号：US12165756

    申请日：2008-07-01

    申请人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

    发明人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

    IPC分类号： H01L21/31 ,  H01L27/08

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7833 ,  H01L29/7843

    摘要： By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

    摘要翻译： 通过在不同应力的接触蚀刻停止层上形成缓冲材料，随后沉积另外的应力诱导材料，可以实现增强的整体器件性能，其中附加应力诱导层的不期望的影响可能在器件区域中减小， 例如，通过去除附加材料或通过进行松弛植入工艺。 此外，在用于形成接触开口的图案化顺序期间的工艺均匀性可以通过在要形成接触开口的区域部分去除附加的应力诱导层来增强。

    Method of forming a field effect transistor comprising a stressed channel region
    7.
    发明申请
    Method of forming a field effect transistor comprising a stressed channel region 失效
    形成包括应力沟道区域的场效应晶体管的方法

    公开(公告)号：US20060076652A1

    公开(公告)日：2006-04-13

    申请号：US11125046

    申请日：2005-05-09

    申请人： Joerg Hohage ,  Hartmut Ruelke ,  Kai Frohberg

    发明人： Joerg Hohage ,  Hartmut Ruelke ,  Kai Frohberg

    IPC分类号： H01L23/58 ,  H01L21/469

    CPC分类号： H01L29/7843 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/665

    摘要： A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, tensile stress is created in the channel region. The tensile stress leads to an increase of the electron mobility in the channel region.

    摘要翻译： 半导体结构包括形成在衬底中的晶体管元件。 应力层形成在晶体管元件上。 应力层具有约900MPa以上的预定拉伸内应力。 由于这种高的固有应力，应力层对晶体管元件的沟道区域施加相当大的弹性力。 因此，在通道区域中产生拉伸应力。 拉伸应力导致通道区域中电子迁移率的增加。

    Non-insulating stressed material layers in a contact level of semiconductor devices
    9.
    发明授权
    Non-insulating stressed material layers in a contact level of semiconductor devices 有权
    非绝缘应力材料层在半导体器件的接触电平

    公开(公告)号：US08450172B2

    公开(公告)日：2013-05-28

    申请号：US12823660

    申请日：2010-06-25

    申请人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

    发明人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

    IPC分类号： H01L21/8238 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

    摘要： In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.

    摘要翻译： 在复杂的半导体器件中，可以在接触电平中使用具有非常高的内部应力水平的非绝缘材料，以便增强诸如场效应晶体管的电路元件的性能，其中非绝缘材料可以被适当地“封装” 介电材料。 因此，可以基于减小的层厚度获得期望的高应变水平，同时仍然提供接触水平所需的绝缘特性。