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1.发明授权Storage element for controlling a logic circuit, and a logic device having an array of such storage elements 有权用于控制逻辑电路的存储元件和具有这种存储元件阵列的逻辑器件公开(公告)号：US07701248B2
公开(公告)日：2010-04-20
申请号：US12100406
申请日：2008-04-10
IPC分类号： G06F7/38 , H03K19/173 , G11C7/00
CPC分类号： H03K17/693 , G11C16/0433 , G11C16/26
摘要： The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.
摘要翻译： 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。 第一和第二非易失性存储单元中的每一个用于存储与另一个相反的状态。 解复用器具有输入，开关输入和两个输出。 输出节点连接到解复用器的输入端。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。
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2.发明申请STORAGE ELEMENT FOR CONTROLLING A LOGIC CIRCUIT, AND A LOGIC DEVICE HAVING AN ARRAY OF SUCH STORAGE ELEMENTS 有权用于控制逻辑电路的存储元件以及具有这种存储元件阵列的逻辑器件公开(公告)号：US20090256590A1
公开(公告)日：2009-10-15
申请号：US12100406
申请日：2008-04-10
IPC分类号： H03K19/0944 , G11C16/04
CPC分类号： H03K17/693 , G11C16/0433 , G11C16/26
摘要： The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.
摘要翻译： 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。第一和第二非易失性存储器单元中的每一个用于存储与另一个相反的状态。 复用器具有输入，开关输入和两个输出。 输出节点连接到多路复用器的输入。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。
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公开(公告)号：US10147349B2
公开(公告)日：2018-12-04
申请号：US15596951
申请日：2017-05-16
申请人： Darwin Hu , Tsung-Lu Syu
发明人： Darwin Hu , Tsung-Lu Syu
摘要： Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various display applications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived brightness level of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described.
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公开(公告)号：US07786749B1
公开(公告)日：2010-08-31
申请号：US12468762
申请日：2009-05-19
申请人： Tsung-Lu Syu , Wilson Kaming Yee
发明人： Tsung-Lu Syu , Wilson Kaming Yee
IPC分类号： H03K19/00 , H03K19/173 , H01L25/00
CPC分类号： G01R31/318516 , H03K19/17736
摘要： A programmable integrated circuit has a plurality of logic elements with each logic element having a plurality of input leads and at least one output lead. The programmable integrated circuit further comprises a group of interconnect lines, and a first set of programmable circuits for electrically connecting the input and output leads of the plurality of logic elements to each other through the group of interconnect lines. The programmable integrated circuit further comprises a test circuit having at least one input and one output. Further the programmable integrated circuit comprises a second set of programmable circuits for electrically connecting the one output of the test circuit to the plurality of input leads of each of the plurality of logic elements and for electrically connecting the at least one output lead of each of the plurality of logic elements to the one input of the test circuit, through the group of interconnect lines.
摘要翻译： 可编程集成电路具有多个逻辑元件，每个逻辑元件具有多个输入引线和至少一个输出引线。 可编程集成电路还包括一组互连线，以及第一组可编程电路，用于通过该组互连线将多个逻辑元件的输入和输出引线彼此电连接。 可编程集成电路还包括具有至少一个输入和一个输出的测试电路。 此外，可编程集成电路包括第二组可编程电路，用于将测试电路的一个输出电连接到多个逻辑元件中的每一个的多个输入引线，并且用于将每个的每个的至少一个输出引线电连接 多个逻辑元件连接到测试电路的一个输入端，通过一组互连线。
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公开(公告)号：US07486572B2
公开(公告)日：2009-02-03
申请号：US11452439
申请日：2006-06-14
申请人： Xiao Luo , Tsung-Lu Syu
发明人： Xiao Luo , Tsung-Lu Syu
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.
摘要翻译： 提供了在待机模式或操作模式下操作的静态随机存取存储器的电压调节器。 电压调节器包括用于产生参考电压的参考电压产生电路，连接到参考电压发生电路的第一控制电路，用于在SRAM的待机模式期间提供电源;以及第二控制电路，连接到参考电压产生电路 用于在SRAM的操作模式期间响应于使能信号而提供功率。
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公开(公告)号：US5631577A
公开(公告)日：1997-05-20
申请号：US668276
申请日：1996-06-21
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/173 , H03K19/177 , G11C13/00
CPC分类号： H03K19/1736 , G11C7/1072 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/17704
摘要： A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.
摘要翻译： 双端口模式下的可配置逻辑块（CLB）使用一个地址将相同的信息写入第一个RAM和第二个RAM。 提供给第二函数发生器的输入信号可以用于独立于写入操作而非甚至异步地读取，从而显着地增加使用两组RAM的应用速度。 同步模式下的CLB锁存适当的地址和数据信号，并产生选通的写使能信号。 选通信号是自定时的，即写入操作是完全自动的，从而确保写操作在一个时钟周期内发生。
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公开(公告)号：US09653015B2
公开(公告)日：2017-05-16
申请号：US14340999
申请日：2014-07-25
申请人： Darwin Hu , Tsung-Lu Syu
发明人： Darwin Hu , Tsung-Lu Syu
CPC分类号： G09G3/2074 , G09G3/2014 , G09G3/3607 , G09G3/3614 , G09G3/3648 , G09G2300/0804 , G09G2300/0842 , G09G2300/0857 , G09G2330/025
摘要： Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various projection applications, storage and optical communications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. These sub-image elements are driven by PWM as in digital modulation. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived effect of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described.
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公开(公告)号：US20170249891A1
公开(公告)日：2017-08-31
申请号：US15596951
申请日：2017-05-16
申请人： Darwin Hu , Tsung-Lu Syu
发明人： Darwin Hu , Tsung-Lu Syu
CPC分类号： G09G3/2074 , G09G3/2014 , G09G3/3607 , G09G3/3614 , G09G3/3648 , G09G2300/0804 , G09G2300/0842 , G09G2300/0857 , G09G2330/025
摘要： Architecture and designs of display devices are described, where the display devices possesses high spatial resolution as well as high intensity resolution and may be readily used in various display applications. According to one aspect of the present invention, a display device includes an array of image elements, each of the image elements further includes an array of sub-image elements. A portion of an image element area, namely some of the sub-image elements, is turned on, which has the same perceived brightness level of turning on an entire image element for a specific time. In addition, various designs of an image element or a sub-image element are described.
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公开(公告)号：US20070070718A1
公开(公告)日：2007-03-29
申请号：US11452439
申请日：2006-06-14
申请人： Xiao Luo , Tsung-Lu Syu
发明人： Xiao Luo , Tsung-Lu Syu
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.
摘要翻译： 提供了在待机模式或操作模式下操作的静态随机存取存储器的电压调节器。 电压调节器包括用于产生参考电压的参考电压产生电路，连接到参考电压发生电路的第一控制电路，用于在SRAM的待机模式期间提供电源;以及第二控制电路，连接到参考电压产生电路 用于在SRAM的操作模式期间响应于使能信号而提供功率。
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公开(公告)号：US5566123A
公开(公告)日：1996-10-15
申请号：US386972
申请日：1995-02-10
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/173 , H03K19/177 , G11C7/00
CPC分类号： H03K19/1736 , G11C7/1072 , G11C7/22 , G11C8/00 , G11C8/16 , H03K19/17704
摘要： A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.
摘要翻译： 双端口模式下的可配置逻辑块（CLB）使用一个地址将相同的信息写入第一个RAM和第二个RAM。 提供给第二函数发生器的输入信号可以用于独立于写入操作而非甚至异步地读取，从而显着地增加使用两组RAM的应用速度。 同步模式下的CLB锁存适当的地址和数据信号，并产生选通的写使能信号。 选通信号是自定时的，即写入操作是完全自动的，从而确保写操作在一个时钟周期内发生。
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