公开(公告)号：US07701248B2

公开(公告)日：2010-04-20

申请号：US12100406

申请日：2008-04-10

申请人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

发明人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

IPC分类号： G06F7/38 ,  H03K19/173 ,  G11C7/00

CPC分类号： H03K17/693 ,  G11C16/0433 ,  G11C16/26

摘要： The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

摘要翻译： 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。 第一和第二非易失性存储单元中的每一个用于存储与另一个相反的状态。 解复用器具有输入，开关输入和两个输出。 输出节点连接到解复用器的输入端。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。

公开(公告)号：US20090256590A1

公开(公告)日：2009-10-15

申请号：US12100406

申请日：2008-04-10

申请人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

发明人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

IPC分类号： H03K19/0944 ,  G11C16/04

CPC分类号： H03K17/693 ,  G11C16/0433 ,  G11C16/26

摘要： The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A multiplexer has an input, a switched input and two outputs. The output node is connected to the input of the multiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

摘要翻译： 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。第一和第二非易失性存储器单元中的每一个用于存储与另一个相反的状态。 复用器具有输入，开关输入和两个输出。 输出节点连接到多路复用器的输入。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。

公开(公告)号：US06927993B2

公开(公告)日：2005-08-09

申请号：US10642079

申请日：2003-08-14

申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8236 ,  H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 栅极间隔开并且至少与通道的第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US06834009B1

公开(公告)日：2004-12-21

申请号：US10641803

申请日：2003-08-15

申请人： Kai Man Yue ,  Bomy Chen

发明人： Kai Man Yue ,  Bomy Chen

IPC分类号： G11C1604

CPC分类号： H03K19/17748 ,  H03K19/1778

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase. In addition a MOS FET transistor connects the gate of the MOS transistor to a voltage when the non-volatile memory cell is turned off. The floating gate of the non-volatile memory cell is connected to the gate of the MOS FET transistor.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有第一区域和第二区域的分离栅极类型，其间具有沟道。 电池具有位于通道第一部分上方的浮动栅极，该第一部分与第一区域相邻，并且控制栅极位于与第二区域相邻的通道的第二部分上方。 第二区域连接到MOS晶体管的栅极。 通过热电子注入机制将电子从通道注入到浮动栅上来编程电池。 Fowler-Nordheim将电池从浮动栅极隧穿到控制栅极，从而消除电池。 因此，在编程或擦除期间，不会对第二区域施加高电压。 此外，MOS FET晶体管将MOS晶体管的栅极连接到非易失性存储单元关断时的电压。 非易失性存储单元的浮置栅极连接到MOS FET晶体管的栅极。

公开(公告)号：US06756632B1

公开(公告)日：2004-06-29

申请号：US10641609

申请日：2003-08-15

申请人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

发明人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

IPC分类号： H01L29788

CPC分类号： H03K19/17748 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/7885 ,  H03K19/1778

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floating gate positioned over a first portion of the channel and a control gate positioned over a second portion of the channel with electrons being injected onto the floating gate by hot electron injection mechanism. The nonvolatile memory cell is erased by the action of the electrons from the floating gate being tunneled through Fowler-Nordheim tunneling onto the control gate, which is adjacent to the second region. As a result, no high voltage is ever applied to the second region during program or erase. Thus, the nonvolatile memory cell with the second region can be connected directly to the gate of the MOS transistor, which together therewith forms a nonvolatile reprogrammable switch.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有位于通道的第一部分上方的浮动栅极的分离栅极型，以及位于通道的第二部分上方的控制栅极，其中电子通过热电子注入机制注入浮置栅极。 非易失性存储单元被来自浮动栅极的电子的作用擦除，通过Fowler-Nordheim隧穿隧道穿过与第二区域相邻的控制栅极。 因此，在编程或擦除期间，不会对第二区域施加高电压。 因此，具有第二区域的非易失性存储单元可以直接连接到MOS晶体管的栅极，其一起形成非易失性可编程开关。

公开(公告)号：US06992909B2

公开(公告)日：2006-01-31

申请号：US11157318

申请日：2005-06-20

申请人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

发明人： Bomy Chen ,  Kai Man Yue ,  Dana Lee ,  Feng Gao

IPC分类号： G11C17/00

CPC分类号： H01L27/112 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/1126 ,  H01L27/11266

摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.

摘要翻译： 多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。 每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 门间隔开并与通道的至少第二部分绝缘。 每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻 第一区域和/或与第二区域相邻的通道的第三部分。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。 同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。 最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

公开(公告)号：US06870233B2

公开(公告)日：2005-03-22

申请号：US10642077

申请日：2003-08-14

申请人： Bomy Chen ,  Kai Man Yue ,  Andrew Chen

发明人： Bomy Chen ,  Kai Man Yue ,  Andrew Chen

IPC分类号： G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8236 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/11266 ,  G11C11/5671 ,  G11C11/5692 ,  G11C17/123 ,  H01L27/112

摘要： A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

摘要翻译： 多位只读存储器（ROM）单元具有第一导电类型的具有第一浓度的半导体衬底。 彼此间隔开的第二导电类型的第一和第二区域在衬底中。 通道在第一和第二区域之间。 通道具有三个部分，第一部分，第二部分和第三部分。 栅极间隔开并且至少与通道的第二部分绝缘。 ROM单元具有多个N个可能状态中的一个，其中N大于2. ROM单元的可能状态由存在或不存在在通道的第一部分中形成的延伸或光晕而相邻 到与第二区域相邻的第一区域和/或在该通道的第三部分中。 在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。

公开(公告)号：US07403418B2

公开(公告)日：2008-07-22

申请号：US11241582

申请日：2005-09-30

申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

公开(公告)号：US07358559B2

公开(公告)日：2008-04-15

申请号：US11239791

申请日：2005-09-29

申请人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

发明人： Felix (Ying-Kit) Tsui ,  Jeng-Wei Yang ,  Bomy Chen ,  Chun-Ming Chen ,  Dana Lee ,  Changyuan Chen

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

摘要翻译： 双向读/写非易失性存储单元和阵列能够实现高密度。 每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。 电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。 浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。 控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。 通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。 双向读取允许将单元编程为存储位，每个浮动栅极中有一位。 这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。 相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。 相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

公开(公告)号：US07351613B2

公开(公告)日：2008-04-01

申请号：US10983314

申请日：2004-11-04

申请人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

发明人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC分类号： H01L21/82

CPC分类号： H01L28/20 ,  H01C17/267 ,  H01L22/22

摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

摘要翻译： 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。