公开(公告)号：US08553478B2

公开(公告)日：2013-10-08

申请号：US13190169

申请日：2011-07-25

Applicant: Tae Sik Yun ,  Kang Seol Lee

Inventor： Tae Sik Yun ,  Kang Seol Lee

IPC: G11C7/00

CPC classification number: G11C29/883 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.

Abstract translation: 半导体集成电路包括与第一芯片堆叠在一起的第一芯片和第二芯片。 在第二芯片上形成第一存储区域，并且在第一芯片上形成用于修复第一存储区域的故障的第二存储区域。

公开(公告)号：US07969800B2

公开(公告)日：2011-06-28

申请号：US12493734

申请日：2009-06-29

Applicant: Tae Sik Yun ,  Kang Seol Lee

Inventor： Tae Sik Yun ,  Kang Seol Lee

IPC: G11C7/00

CPC classification number: G11C8/18

Abstract: A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.

Abstract translation: 一种半导体存储装置，包括：行路径激活部，被配置为根据接收到的地址和主动命令生成线路连接控制信号。 半导体存储装置还包括一个单元阵列电路单元，包括用于连接单元块中的第一输入/输出线和延伸到单元块外部的第二输入/输出线的输入/输出线开关。 单元阵列还包括用于将位线对彼此连接的位线开关。 输入/输出线路开关和位线开关进一步由来自行路径激活单元的线路连接控制信号控制。

公开(公告)号：US07898287B2

公开(公告)日：2011-03-01

申请号：US12291731

申请日：2008-11-13

Applicant: Ki Ho Kim ,  Kang Seol Lee

Inventor： Ki Ho Kim ,  Kang Seol Lee

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/00323 ,  H03K19/018564

Abstract: An input buffer includes a delay compensation unit for combining (a) a first signal obtained by buffering an input signal using another signal, which is out of phase with the input signal, with (b) a second signal obtained by buffering the input signal using a reference voltage signal, to output a third signal.

Abstract translation: 输入缓冲器包括延迟补偿单元，用于组合（a）通过使用与输入信号异相的另一信号来缓冲输入信号而获得的第一信号，（b）通过使用 参考电压信号，以输出第三信号。

公开(公告)号：US07545199B2

公开(公告)日：2009-06-09

申请号：US10980408

申请日：2004-11-03

Applicant: Kang Seol Lee ,  Yong Mi Kim

Inventor： Kang Seol Lee ,  Yong Mi Kim

IPC: G11C5/14

CPC classification number: G11C11/4074 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/075

Abstract: Disclosed are a power supply circuit for an oscillator of a semiconductor memory device and a voltage pumping device using the same. In the power supply circuit, a voltage divider divides a voltage between an external power supply and ground. A driver is controlled by a signal of the voltage divided by the voltage divider. The driver supplies an internal power supply voltage. A capacitor is coupled between the driver and the ground. As the level of an external power supply voltage is increased, a relatively low voltage is supplied to the oscillator to increase a cycle length of an output pulse signal of the oscillator. Therefore, an excessive increase in the internal power supply voltage due to over-pumping can be avoided and noise occurrence and electric current consumption can be reduced.

Abstract translation: 公开了一种用于半导体存储器件的振荡器的电源电路和使用该电源的电压泵送装置。 在电源电路中，分压器分隔外部电源和地之间的电压。 驱动器由分压器分压的信号控制。 驱动器提供内部电源电压。 电容器连接在驱动器和地之间。 随着外部电源电压的电平升高，向振荡器提供相对低的电压以增加振荡器的输出脉冲信号的周期长度。 因此，可以避免由于过度泵浦引起的内部电源电压的过度增加，并且可以降低噪声发生和电流消耗。

公开(公告)号：US06885605B2

公开(公告)日：2005-04-26

申请号：US10255999

申请日：2002-09-26

Applicant: Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

Inventor： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

IPC: H03K19/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4193

CPC classification number: G11C11/4074 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/2227

Abstract: A power-up signal generator uses a deep power down power-up signal, which should be in a standby state in a deep power down entry, for an initialization of other semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage. The generator may include a power-up detector for generating a power-up detection signal, a deep power down power-up signal generator for generating a deep power down power-up signal, a power-up signal generator for generating a power-up signal and a power-up controller for determining whether or not to enable the power-up signal in the deep power down entry.

Abstract translation: 上电信号发生器使用深度掉电加电信号，其将处于深功率下降条目中的待机状态，用于在内部电源电压为内部操作的DRAM器件中的其它半导体元件的初始化 生成。 发电机还使用上电信号，该信号在深度掉电输入中被禁用，并通过内部电源电压在深度断电输出中使能。 该发生器可以包括用于产生上电检测信号的上电检测器，用于产生深度掉电上电信号的深度断电上电信号发生器，用于产生上电的上电信号发生器 信号和上电控制器，用于确定是否在深度断电输入中启用上电信号。

公开(公告)号：US08837191B2

公开(公告)日：2014-09-16

申请号：US13167963

申请日：2011-06-24

Applicant: Heat Bit Park ,  Kang Seol Lee

Inventor： Heat Bit Park ,  Kang Seol Lee

IPC: G11C5/06

CPC classification number: G06F13/385

Abstract: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.

Abstract translation: 半导体装置包括多芯片模块，该多芯片模块包括第一芯片和第二芯片。 半导体装置包括第一芯片中的第一数据线，以承载第一读取数据; 第一芯片中的第一控制器被配置为基于从第一数据线发送的第一读取数据在第一芯片中的第一输出数据线上生成第一输出数据; 第一数据发射机，被配置为将所述第一输出数据线电连接到所述第二芯片。

公开(公告)号：US08400136B2

公开(公告)日：2013-03-19

申请号：US12198562

申请日：2008-08-26

Applicant: Kang Seol Lee

Inventor： Kang Seol Lee

IPC: G05F3/16

CPC classification number: G05F3/267 ,  G06F17/5068

Abstract: A semiconductor device and a layout method of the same reduce a mismatch in a semiconductor device. The semiconductor device includes a first transistor unit providing a first path of current and a second transistor unit designed in a mirror structure to the first transistor unit and providing a second path of current. The layout of the second transistor unit has a shape identical to the first transistor unit and shifted in a first direction. The layout of the semiconductor device reduces a mismatch of the transistors occurring when masks are combined, and thereby reduces their offset.

Abstract translation: 半导体器件及其布置方法减少半导体器件中的失配。 该半导体器件包括提供电流的第一路径的第一晶体管单元和以第一晶体管单元的镜结构设计并提供第二电流路径的第二晶体管单元。 第二晶体管单元的布局具有与第一晶体管单元相同的形状并沿第一方向移位。 半导体器件的布局减少了当掩模组合时发生的晶体管的失配，从而减小它们的偏移。

公开(公告)号：US20100232239A1

公开(公告)日：2010-09-16

申请号：US12493734

申请日：2009-06-29

Applicant: Tae Sik Yun ,  Kang Seol Lee

Inventor： Tae Sik Yun ,  Kang Seol Lee

IPC: G11C7/00

CPC classification number: G11C8/18

Abstract: A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.

Abstract translation: 一种半导体存储装置，包括：行路径激活部，被配置为根据接收到的地址和主动命令生成线路连接控制信号。 半导体存储装置还包括一个单元阵列电路单元，包括用于连接单元块中的第一输入/输出线和延伸到单元块外部的第二输入/输出线的输入/输出线开关。 单元阵列还包括用于将位线对彼此连接的位线开关。 输入/输出线路开关和位线开关进一步由来自行路径激活单元的线路连接控制信号控制。

公开(公告)号：US07446577B2

公开(公告)日：2008-11-04

申请号：US11154870

申请日：2005-06-16

Applicant: Jae Il Kim ,  Kang Seol Lee

Inventor： Jae Il Kim ,  Kang Seol Lee

IPC: H03B1/00

CPC classification number: H03K17/302 ,  H03K17/145 ,  H03K17/223 ,  H03K17/693

Abstract: Disclosed is a controller for driving current of a semiconductor device having an over-driving function, the controller comprising: a load means supplied with an internal voltage; a plurality of switching means, each of which has a first terminal connected to an external voltage and a second terminal connected to the load means, wherein at least one of the plurality of switching means is selectively turned on/off according to an voltage level of the external voltage.

Abstract translation: 公开了一种用于驱动具有过驱动功能的半导体器件的电流的控制器，该控制器包括：被提供内部电压的负载装置; 多个开关装置，每个开关装置具有连接到外部电压的第一端子和连接到所述负载装置的第二端子，其中，所述多个开关装置中的至少一个根据所述多个开关装置的电压电平选择性地导通/ 外部电压。

公开(公告)号：US20080225605A1

公开(公告)日：2008-09-18

申请号：US11963434

申请日：2007-12-21

Applicant: Kang Seol Lee ,  Eun Souk Lee

Inventor： Kang Seol Lee ,  Eun Souk Lee

IPC: G11C7/06

CPC classification number: H01L27/092 ,  H01L27/0207

Abstract: A latch structure includes a first inverter that includes a first PMOS transistor and a first NMOS transistor, and a second inverter that includes a second PMOS transistor and a second NMOS transistor, receives an output signal of the first inverter, and outputs an input signal to the first inverter. The sources of the first and second transistors of the same type are connected to a common straight source line.

Abstract translation: 锁存结构包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管，接收第一反相器的输出信号，并将输入信号输出到 第一台逆变器。 相同类型的第一和第二晶体管的源极连接到公共直线源极线。