公开(公告)号：US06885605B2

公开(公告)日：2005-04-26

申请号：US10255999

申请日：2002-09-26

申请人： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

发明人： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

IPC分类号： H03K19/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4193

CPC分类号： G11C11/4074 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/2227

摘要： A power-up signal generator uses a deep power down power-up signal, which should be in a standby state in a deep power down entry, for an initialization of other semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage. The generator may include a power-up detector for generating a power-up detection signal, a deep power down power-up signal generator for generating a deep power down power-up signal, a power-up signal generator for generating a power-up signal and a power-up controller for determining whether or not to enable the power-up signal in the deep power down entry.

摘要翻译： 上电信号发生器使用深度掉电加电信号，其将处于深功率下降条目中的待机状态，用于在内部电源电压为内部操作的DRAM器件中的其它半导体元件的初始化 生成。 发电机还使用上电信号，该信号在深度掉电输入中被禁用，并通过内部电源电压在深度断电输出中使能。 该发生器可以包括用于产生上电检测信号的上电检测器，用于产生深度掉电上电信号的深度断电上电信号发生器，用于产生上电的上电信号发生器 信号和上电控制器，用于确定是否在深度断电输入中启用上电信号。

公开(公告)号：US07382677B2

公开(公告)日：2008-06-03

申请号：US11544284

申请日：2006-10-06

申请人： Kang Seol Lee ,  Kee Teok Park

发明人： Kang Seol Lee ,  Kee Teok Park

IPC分类号： G11C7/00

CPC分类号： G11C5/147 ,  G11C5/143

摘要： A internal voltage generator in a semiconductor memory device has a first and second internal voltage generators. The first internal voltage generator outputs a first signal having a first voltage level to internal circuits of the memory device during an active mode of the memory device operation. The second internal voltage generator outputs a second signal having a second voltage level to the internal circuits of the memory device; however, the second signal is interrupted in absence of a predetermined level of a power control signal during the active mode of the memory device operation. The internal voltage control unit monitors the operational signals generated by the memory device and outputs the predetermined level of the power control signal during a plurality of active sections of the active mode of the memory device operation requiring power.

摘要翻译： 半导体存储器件中的内部电压发生器具有第一和第二内部电压发生器。 第一内部电压发生器在存储器件操作的活动模式期间向存储器件的内部电路输出具有第一电压电平的第一信号。 第二内部电压发生器向存储器件的内部电路输出具有第二电压电平的第二信号; 然而，在存储器件操作的活动模式期间，在没有功率控制信号的预定电平的情况下，第二信号被中断。 内部电压控制单元监视存储器件产生的操作信号，并且在需要电力的存储器件操作的活动模式的多个有效部分期间输出功率控制信号的预定电平。

公开(公告)号：US07193906B2

公开(公告)日：2007-03-20

申请号：US11008672

申请日：2004-12-10

申请人： Ji Eun Jang ,  Kee Teok Park

发明人： Ji Eun Jang ,  Kee Teok Park

IPC分类号： G11C5/14

CPC分类号： G11C29/021 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/028 ,  G11C2029/5004

摘要： Provided is concerned with a voltage regulation circuit and method of regulating the voltage, including a reference voltage generator for generating a reference voltage by dividing a core voltage of a semiconductor memory device, a controller for controlling the reference voltage generator to adjust the reference voltage without handling the core voltage in response to a test signal of a test mode, and a voltage generator for generating a bit-line precharging voltage and/or a cell plate voltage in accordance with the reference voltage.

摘要翻译： 关于电压调节电路和调节电压的方法，包括用于通过划分半导体存储器件的芯电压来产生参考电压的参考电压发生器，用于控制参考电压发生器的控制器，以在没有 响应于测试模式的测试信号处理核心电压;以及电压发生器，用于根据参考电压产生位线预充电电压和/或单元板电压。

公开(公告)号：US06967880B2

公开(公告)日：2005-11-22

申请号：US10236313

申请日：2002-09-06

申请人： Kee Teok Park

发明人： Kee Teok Park

IPC分类号： G11C29/00 ,  G11C29/34 ,  H01L27/105 ,  H01L31/0328

CPC分类号： H01L27/105 ,  G11C29/34

摘要： A semiconductor memory test device is capable of reducing the test time and increasing test reliability by applying an effective stress in a burn-in level or a wafer level. The semiconductor memory test device controls a sense amplifier using an additional sense amplifier driving signal when a 2rb pattern stress is applied. Therefore, the semiconductor memory test device applies a uniform stress by applying the constant supply voltage to a cell corresponding to the entire wordlines.

摘要翻译： 半导体存储器测试装置能够通过在老化级或晶片级施加有效应力来减少测试时间并提高测试的可靠性。 当施加2rb图案应力时，半导体存储器测试装置使用附加的读出放大器驱动信号来控制读出放大器。 因此，半导体存储器测试装置通过将恒定电源电压施加到对应于整个字线的单元来施加均匀的应力。

公开(公告)号：US06683445B2

公开(公告)日：2004-01-27

申请号：US10094639

申请日：2002-03-12

申请人： Kee Teok Park

发明人： Kee Teok Park

IPC分类号： G05F316

CPC分类号： G05F1/465

摘要： An internal power voltage generator for achieving stable operation of a semiconductor device by selectively connecting an external power voltage terminal to a supply line of an internal power voltage in an operation power potential range of the semiconductor device, and generating a predetermined reference voltage in a reference voltage generator in accordance with the internal power voltage after a predetermined potential.

摘要翻译： 一种内部电力电压发生器，用于通过选择性地将外部电源电压端子连接到半导体器件的操作电力电位范围内的内部电源电压的电源线，并且在参考中产生预定参考电压来实现半导体器件的稳定操作 电压发生器按照预定电位后的内部电源电压。

公开(公告)号：US07075833B2

公开(公告)日：2006-07-11

申请号：US10872346

申请日：2004-06-18

申请人： Khil Ohk Kang ,  Kee Teok Park

发明人： Khil Ohk Kang ,  Kee Teok Park

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C2029/1202 ,  G11C2029/5004

摘要： The present invention discloses a circuit for detecting a negative word line voltage including a detecting unit for detecting a negative word line voltage in a detection node by using a plurality of loads coupled in series between a power supply terminal and a negative word line voltage terminal, a test signal generating unit for generating a plurality of test signals for detecting variations of the negative word line voltage, and a control unit driven according to the test signals, for controlling a potential of the detection node by adjusting a number of the loads of the detecting unit. The circuit for detecting the negative word line voltage can detect a wanted level of negative word line voltage by using the plurality of test signals without modifying the circuit, to reduce a development period of DRAM semiconductor products.

摘要翻译： 本发明公开了一种用于检测负字线电压的电路，包括检测单元，用于通过使用串联耦合在电源端子和负字线电压端子之间的多个负载来检测检测节点中的负字线电压， 测试信号产生单元，用于产生用于检测负字线电压的变化的多个测试信号，以及根据测试信号驱动的控制单元，用于通过调整检测节点的数量来控制检测节点的电位 检测单元。 用于检测负字线电压的电路可以通过使用多个测试信号来检测负字线电压的有用电平而不修改电路，以减少DRAM半导体产品的显影周期。

公开(公告)号：US06850453B2

公开(公告)日：2005-02-01

申请号：US10330579

申请日：2002-12-27

申请人： Kee Teok Park

发明人： Kee Teok Park

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C5/147

摘要： A deep power down control circuit includes a deep power down switch unit to separate an external power voltage line from a selected one of a plurality of internal power voltage lines according to a deep power down signal, a deep power down discharge unit for connecting the plurality of internal power voltage lines to a ground voltage line and to discharge them to a ground voltage level according to the deep power down signal. The deep power down control circuit also includes a deep power down signal generating unit control according to a bank active detect signal and a burst end command, to output the deep power down signal by using a clock enable signal. The deep power down control circuit connects the plurality of internal power voltage lines to the ground voltage line, and thus prevents floating to remove the possibility of inversion of the power voltage or generation of the latch-up. Moreover, the deep power down control circuit prevents leakage current by a micro bridge among the plurality of internal power voltage lines.

摘要翻译： 深度断电控制电路包括：深度断电开关单元，用于根据深度掉电信号将外部电源电压线与多个内部电力电压线中的所选择的一个分离;深度放电放电单元，用于连接多个 的内部电源电压线到地电压线，并根据深度掉电信号将其放电到接地电压电平。 深度掉电控制电路还包括根据存储体有效检测信号和突发结束命令的深度掉电信号生成单元控制，以通过使用时钟使能信号来输出深度掉电信号。 深度断电控制电路将多条内部电源电压线连接到地电压线，从而防止浮动以消除电源电压反转或产生闩锁的可能性。 此外，深度断电控制电路防止多个内部电力电压线中的微电桥的漏电流。

公开(公告)号：US08867282B2

公开(公告)日：2014-10-21

申请号：US13339183

申请日：2011-12-28

申请人： Tae Sik Yun ,  Kee Teok Park

发明人： Tae Sik Yun ,  Kee Teok Park

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/24 ,  G11C11/4099 ,  G11C29/12 ,  G11C11/401

CPC分类号： G11C11/4099 ,  G11C11/401 ,  G11C29/24 ,  G11C2029/1202

摘要： A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.

摘要翻译： 具有开放位线结构的半导体装置包括：存储体，包括多个存储单元块和形成有多个位线的虚拟垫;配置为布置在多个存储单元块之间的位线读出放大器 和虚拟垫，比较位线和互补位线之间的电压差，并放大差值;虚拟字线驱动单元，被配置为响应于测试模式选择性地激活虚拟垫的虚拟字线。

公开(公告)号：US07193920B2

公开(公告)日：2007-03-20

申请号：US11169949

申请日：2005-06-30

申请人： Sang Jin Byeon ,  Kee Teok Park

发明人： Sang Jin Byeon ,  Kee Teok Park

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： A semiconductor memory device generates a control signal for regulating a potential of an internal power voltage when an extended mode register is set to adjust an operating speed and a tWR (time to write recovery) of a chip. The semiconductor memory device comprises an extended mode register setting unit and an internal power voltage generating unit. When an internal circuit enters into a specific mode for high-speed operation, the extended mode register setting unit outputs a plurality of internal power control signals to regulate a potential of an internal power voltage of the internal circuit. The internal power voltage generating unit generates an internal power voltage by regulating the potential of the internal power voltage in response to the plurality of internal power control signals.

摘要翻译： 当扩展模式寄存器被设置以调整芯片的操作速度和tWR（写入恢复时间）时，半导体存储器件产生用于调节内部电源电压的电位的控制信号。 半导体存储器件包括扩展模式寄存器设置单元和内部电源电压产生单元。 当内部电路进入用于高速运行的特定模式时，扩展模式寄存器设置单元输出多个内部功率控制信号以调节内部电路的内部电源电压的电位。 内部电力电压产生单元通过响应于多个内部功率控制信号调节内部电力电压的电位而产生内部电力电压。

公开(公告)号：US06240025B1

公开(公告)日：2001-05-29

申请号：US09604296

申请日：2000-06-26

申请人： Kee Teok Park

发明人： Kee Teok Park

IPC分类号： G11C700

CPC分类号： G11C5/145 ,  H02M3/073

摘要： A voltage generator is disclosed which has a charge pump unit including a pump transistor for performing a charge pumping operation by a pump control signal from a ring oscillator and a precharge transistor for performing a charge precharge operation by a precharge control signal from the ring oscillator. The voltage generator additionally has a controller which provides a new back-bias control signal by combining the pump control signal from the ring oscillator with the precharge control signal from the ring oscillator and controls a threshold voltage of the precharge transistor with the back-bias control signal.

摘要翻译： 公开了一种电压发生器，其具有电荷泵单元，该电荷泵单元包括用于通过来自环形振荡器的泵控制信号和预充电晶体管执行电荷泵浦操作的泵浦晶体管，用于通过来自环形振荡器的预充电控制信号进行充电预充电操作。 电压发生器还具有控制器，其通过将来自环形振荡器的泵控制信号与来自环形振荡器的预充电控制信号组合来提供新的反向偏置控制信号，并且利用反向偏置控制来控制预充电晶体管的阈值电压 信号。